High-temperature silicon-on-insulator electronics for space nuclear power systems: requirements and feasibility

Fleetwood, D.M.; Thome, F.V.; Tsao, S. S.; Dressendorfer, P. V.; Dandini, V.J.; Schwank, J.R.

doi:10.1109/23.7506

Cited by 82 publications

(19 citation statements)

References 69 publications

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“…On the other hand, the contribution of interface traps does not vary with temperature beyond 100"C, so AVt is more positive for 80°C irradiation than for room temperature irradiation due to the decrease of trapped charge contnbution. The fact that annealing of interface traps has not been observed is consistent with a large set of data that shows that annealing occurs for temperatures above 100°C [21,22]. However, previous work [23] reports that interface trap contribution could increase linearly with increasing temperature even in the temperature range of 25-80°C.…”

Section: Test Implication For Mos Devicessupporting

confidence: 80%

Ionizing dose hardness assurance methodology for qualification of a BiCMOS technology dedicated to high dose level applications

Flament¹,

Musseau²,

Leray³

et al.

RADECS 97. Fourth European Conference on Radiation and Its Effects on Components and Systems (Cat. No.97TH8294)

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This work concerns the development of a radiation hardness assurance methodology specially devoted to CMOS, JI'ET and bipolar transistors used in high total dose level environments. On the basis of recent studies, high tempe:rature, high dose rate irradiations were performed. We propose a test procedure which combines high temperature irradiations and isochronal anneals for the qualification. 0-7803-4071-X/98/$'10.00 0 1998 IEEE.

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Section: Test Implication For Mos Devicessupporting

confidence: 80%

Ionizing dose hardness assurance methodology for qualification of a BiCMOS technology dedicated to high dose level applications

Flament¹,

Musseau²,

Leray³

et al.

RADECS 97. Fourth European Conference on Radiation and Its Effects on Components and Systems (Cat. No.97TH8294)

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show abstract

“…During mixed-mode anneal, the temperature of the EB spacer is not known. However, the temperature near the interface typically must be at least 80-100 C for interface traps to be removed [15], [16], and may well be as high locally as 150 C [5].…”

Section: Calculationmentioning

confidence: 99%

Understanding Radiation- and Hot Carrier-Induced Damage Processes in SiGe HBTs Using Mixed-Mode Electrical Stress

Cheng

Jun²,

Sutton³

et al. 2007

IEEE Trans. Nucl. Sci.

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Using mixed-mode annealing to help evaluate the responses of modern bipolar transistors, we compare the damage processes associated with X-ray irradiation-induced and hot carrier-induced damage in SiGe HBTs. Stress and radiation measurements indicate that the by-products of both X-ray irradiation-induced and hot carrier-induced trap reactions are identical. We use calculations to better understand the operative damage mechanisms, and find that a hydrogen reaction-diffusion model can predict the observed characteristics of our measurements. Calculations indicate that the transport of hydrogen molecules inside the emitter-base oxides determines the trap generation and recovery processes.

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“…Более того, вплоть до 100-125 °С увеличение температуры приводит к ро-сту скорости встраивания ПС [7,39,40]. Реальный от-жиг ПС наблюдается при более высоких температу-рах -как правило, более 150 °С (рис.…”

Section: эффекты длительного низкоинтенсивного облученияunclassified

“…Реальный от-жиг ПС наблюдается при более высоких температу-рах -как правило, более 150 °С (рис. 6 [39]). На рис.…”

Section: эффекты длительного низкоинтенсивного облученияunclassified

“…На рис. 6 [39] показано изменение порогового напряжения ∆V th , а также вкладов в него заряда в оксиде ∆V ot и заряда ПС ∆V it для n−канальных МОП−транзисторов, об-лученных дозой 3 Мрад(Si) и подвергнутых после этого изохронному отжигу при последовательно повышающихся значениях температуры (в течение 30 мин при каждой температуре). Из рис.…”

Section: эффекты длительного низкоинтенсивного облученияunclassified

See 1 more Smart Citation

Low Dose Rate Effects in Silicon Based Devices and Integrated Circuits: A Review

Tapero

2018

Izv. vysš. učebn. zaved., Mater. èlektron. teh.

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High-temperature silicon-on-insulator electronics for space nuclear power systems: requirements and feasibility

Cited by 82 publications

References 69 publications

Ionizing dose hardness assurance methodology for qualification of a BiCMOS technology dedicated to high dose level applications

Ionizing dose hardness assurance methodology for qualification of a BiCMOS technology dedicated to high dose level applications

Understanding Radiation- and Hot Carrier-Induced Damage Processes in SiGe HBTs Using Mixed-Mode Electrical Stress

Low Dose Rate Effects in Silicon Based Devices and Integrated Circuits: A Review

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