In a first part, we revisit the methodology used to calculate the avalanche breakdown voltage of power semiconductor devices. We show that the classical formulations using Van Oversraeten ionisation coefficient can lead to an underestimation of about 45% regarding the voltage handling capability.We next present a review of the major termination techniques used today in microelectronics, mainly planar compatible. Their principle will be shown and some general considerations about their drawbacks and advantages given. A comparison will be given regarding some criteria such as their static and dynamic efficiency, the space used, the voltage range covered, the ease of design and the technological feasibility.