High-voltage thick layer SOI technology for PDP scan driver IC

Qiao, Ming; Jiang, Lingli; Wang, Meng; Liao, Hong; Liang, Ted; Sun, Zheng; Zhang, Bo; Li, Zhaoji; Huang, Guangzuo; Zhao, Yuanyuan; Lai, Li; Hu, Xi; Zhuang, Xiang; Luo, Xiaorong; Wang, Zhuo

doi:10.1109/ispsd.2011.5890820

Cited by 24 publications

(4 citation statements)

References 6 publications

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“…THE silicon-on-insulator lateral double-diffused metaloxide-semiconductor (SOI-LDMOS) is widely adopted in power ICs due to its voltage control and high switching frequency characteristics. [1][2][3] For example, RF power LDMOS is widely used in wireless communication. [4] The breakdown voltage (BV) of reverse blocking and the specific on resistance (R on,sp ) of forward conduction are essential properties for the LDMOS, and the Baliga's figure of merit (FOM) is proposed to evaluate the trade-off relationship between the BV and the R on,sp .…”

Section: Introductionmentioning

confidence: 99%

A super-junction SOI-LDMOS with low resistance electron channel

Chen¹,

Huang²,

Huang³

et al. 2021

Chinese Phys. B

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A novel super-junction LDMOS with low resistance channel (LRC), named LRC-LDMOS based on the silicon-on-insulator (SOI) technology is proposed. The LRC is highly doped on the surface of the drift region, which can significantly reduce the specific on resistance (R on,sp) in forward conduction. The charge compensation between the LRC, N-pillar, and P-pillar of the super-junction are adjusted to satisfy the charge balance, which can completely deplete the whole drift, thus the breakdown voltage (BV) is enhanced in reverse blocking. The three-dimensional (3D) simulation results show that the BV and R on,sp of the device can reach 253 V and 15.5 mΩ ⋅ cm2, respectively, and the Baliga’s figure of merit (FOM = BV 2/R on,sp) of 4.1 MW/cm2 is achieved, breaking through the silicon limit.

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Section: Introductionmentioning

confidence: 99%

A super-junction SOI-LDMOS with low resistance electron channel

Chen¹,

Huang²,

Huang³

et al. 2021

Chinese Phys. B

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“…Silicon-on-insulator (SOI) lateral diffused metal-oxidesemiconductor (LDMOS) devices with dielectric buried layers have broad applications in power IC market due to their excellent isolation capacity and strong immunity to latching effect. [1][2][3][4] In order to achieve better breakdown characteristics for planar LDMOS devices, charge balance principle has been widely used. [5][6][7] Although it has a good effect on improving power figure of merit (FOM), there is no effect on reducing device area.…”

Section: Introductionmentioning

confidence: 99%

Variable-K double trenches SOI LDMOS with high-concentration P-pillar*

Zhu

Chen

2020

Chinese Phys. B

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A variable-K trenches silicon-on-insulator (SOI) lateral diffused metal–oxide–semiconductor field-effect transistor (MOSFET) with a double conductive channel is proposed based on the enhancement of low dielectric constant media to electric fields. The device features variable-K dielectric double trenches and a P-pillar between the trenches (VK DT-P LDMOS). The low-K dielectric layer on the surface increases electric field of it. Adding a variable-K material introduces a new electric field peak to the drift region, so as to optimize electric field inside the device. Introduction of the high-concentration vertical P-pillar between the two trenches effectively increases doping concentration of the drift region and maintains charge balance inside it. Thereby, breakdown voltage (BV) of the device is increased. The double conductive channels provide two current paths that significantly reduce specific on-resistance (R on,sp). Simulation results demonstrate that a 17-μm-length device can achieve a BV of 554 V and a low on-resistance of 13.12 mΩ⋅cm2. The R on,sp of VK DT-P LDMOS is reduced by 78.9% compared with the conventional structure.

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“…Silicon‐on‐insulator (SOI) substrate can offer true dielectric isolation, which eases the integration of power devices and low voltage logic devices in power ICs. Consequently, SOI‐LIGBT devices have been widely used as the power switches in the monolithic integration area, especially in the plasma display panel driver ICs and the switch‐mode power supply ICs [1, 2].…”

Section: Introductionmentioning

confidence: 99%

Model of hot‐carrier degradation for lateral IGBT device on SOI substrate

et al. 2013

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A novel model for hot-carrier degradation in a lateral insulated gate bipolar transistor (IGBT) device on SOI substrate (SOI-LIGBT) is presented. The setup of the model is based on the existing hot-carrier degradation mechanism in a SOI-LIGBT and assisted by a lateral DMOS device on SOI substrate (SOI-LDMOS) with completely the same structure except for the doping type in the drain area. The model parameters have been extracted by the degradation measurement results and the validity of the proposed model in a SOI-LIGBT has been also verified.

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High-voltage thick layer SOI technology for PDP scan driver IC

Cited by 24 publications

References 6 publications

A super-junction SOI-LDMOS with low resistance electron channel

A super-junction SOI-LDMOS with low resistance electron channel

Variable-K double trenches SOI LDMOS with high-concentration P-pillar*

Model of hot‐carrier degradation for lateral IGBT device on SOI substrate

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