Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges

Miyano, Satoru; Moriwaki, Shinichi; Yamamoto, Yoshitaka; Kawasumi, A.; Suzuki, T.; Sakurai, Takayasu; Shinohara, Hirofumi

doi:10.1109/jssc.2012.2237572

Cited by 14 publications

(3 citation statements)

References 6 publications

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“…In general, OpenRAM has reasonable trade-off between the two and can be customized by using an alternate sense amplifiers, decoders, or overall dimensional organization. Table 2 compares the bit-density 65 nm CMOS 0.7700 [19] 45 nm CMOS 0.3300 [12] 40 nm CMOS 0.9400 OpenRAM 45 nm FreePDK45 0.8260 [23] 0.5 um CMOS 0.0036 [18] 0.5 um BiCMOS 0.0020 [16] 0.5 um CMOS 0.0050 OpenRAM 0.5 um SCMOS 0.0050 of OpenRAM against published designs using similar technology nodes. The results show the benefit of technology scaling and that OpenRAM has very good density in both technologies.…”

Section: Resultsmentioning

confidence: 99%

OpenRAM: an open-source memory compiler

Guthaus

Stine

Ataei

et al. 2016

Proceedings of the 35th International Conference on Computer-Aided Design

124

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Computer systems research is often inhibited by the availability of memory designs. Existing Process Design Kits (PDKs) frequently lack memory compilers, while expensive commercial solutions only provide memory models with immutable cells, limited configurations, and restrictive licenses. Manually creating memories can be time consuming and tedious and the designs are usually inflexible. This paper introduces OpenRAM, an open-source memory compiler, that provides a platform for the generation, characterization, and verification of fabricable memory designs across various technologies, sizes, and configurations. It enables research in computer architecture, system-on-chip design, memory circuit and device research, and computer-aided design.

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Section: Resultsmentioning

confidence: 99%

OpenRAM: an open-source memory compiler

Guthaus

Stine

Ataei

et al. 2016

Proceedings of the 35th International Conference on Computer-Aided Design

124

View full text Add to dashboard Cite

show abstract

“…Again, there is the history effect. Considering that SRAM cells usually consume energy on the order of several hundreds of fJ/bit or more in total for volatile read and write [35], [36] (this includes activation of long bit lines and word lines, and peripheral circuitry), the increment of the less than 5 fJ/bit at A = 0.01µm 2 is considered negligible. Fig.…”

Section: B Energy and Delaymentioning

confidence: 99%

A Feasibility Study on Ferroelectric Shadow SRAMs Based on Variability-Aware Design Optimization

Takeuchi

Kobayashi

Hiramoto

2019

IEEE J. Electron Devices Soc.

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“…Although reducing the supply voltage (V DD ) is an effective method to realize energy-efficient static random access memory (SRAM), [1][2][3] leakage current limits the improvement in energy efficiency. 4) Tunnel FET (TFET) is promising for breaking the limitation, since TFETs exhibit a subthreshold swing (SS) of less than 60 mV=dec, [5][6][7][8][9][10][11] which can reduce the leakage current compared with MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

Closed-form analytical model of static noise margin for ultra-low voltage eight-transistor tunnel FET static random access memory

Fuketa¹,

O’uchi²,

Fukuda³

et al. 2016

Jpn. J. Appl. Phys.

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Variations of eight-transistor (8T) tunnel FET (TFET) static random access memory (SRAM) cells at ultra-low supply voltage (V DD) of 0.3 V are discussed. A closed-form analytical model for the static noise margin (SNM) of the TFET SRAM cells is proposed to clarify the dependence of SNM on device parameters and is verified by simulations. The SNM variations caused by process variations are investigated using the proposed model, and we show a requirement for the threshold voltage (V TH) variation in the TFET SRAM design, which indicates that the V TH variation must be reduced as the subthreshold swing becomes steeper. In addition, a feasibility of the TFET SRAM cells operating at V DD = 0.3 V in two different process technologies is evaluated using the proposed model.

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Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges

Cited by 14 publications

References 6 publications

OpenRAM: an open-source memory compiler

OpenRAM: an open-source memory compiler

A Feasibility Study on Ferroelectric Shadow SRAMs Based on Variability-Aware Design Optimization

Closed-form analytical model of static noise margin for ultra-low voltage eight-transistor tunnel FET static random access memory

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