Highly manufacturable ELK integration technology with metal hard mask process for high performance 32nm-node interconnect and beyond

Matsumoto, Susumu; Harada, Taishi; Morinaga, Yasunori; Inagaki, Daisuke; Shibata, Junichi; Tashiro, K.; Konishi, Tatsuya; Iwasaki, Atsushi; Hirao, S.; Tsutsue, M.; Nomura, K.; Seo, K.; Hinomura, Toru; Torazawa, Naoki; Suzuki, Shigeru; Kobayashi, Kojiro; Korogi, Hayato; Okamura, H.; Kanda, Yusuke; Shigetoshi, Takushi; Watanabe, Masaki; Tomiyama, K.; Shimizu, Hirokazu; Matsumoto, M.; Sasaki, Tomoyuki; Hamatani, Tsuyoshi; Hagihara, Kiyomi; Ueda, T.

doi:10.1109/iitc.2010.5510707

Cited by 3 publications

(3 citation statements)

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“…A porous SiOCH low-k film has been introduced to reduce the interconnect capacitance as the LSI generation progress (1)(2). Interconnect capacitance affects on the signal delay (T g ) and the power consumption (P chip ) as shown in equations [1][2] (3), so the interconnect capacitance is required to be reduced effectively by introduction of porous SiOCH low-k film.…”

Section: Introductionmentioning

confidence: 99%

“…T g =R gout f g (aC int l int +bC gin )+R int l int (cC int l int +dC gin ) [1] P chip =α0.5f d f c Σ(C int l int +C tr )V pp 2 +(1-α)L g V pp [2] R gout : CMOS output resistance, C gin : CMOS input capacitance, R int : Interconnect resistance, C int : Interconnect capacitance, l int : Interconnect length and V pp : Supply voltage However, since the porous SiOCH low-k film has larger porosity and higher carbon content than conventional rigid films, its surface is easily damaged by processes during integration as shown in Fig. 1 (4-5).…”

Section: Introductionmentioning

confidence: 99%

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Moisture Uptake Impact on Damage Layer of Porous Low-k Film in 80nm-Pitched Cu Interconnects

et al. 2011

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Impacts of the moisture uptake into the damage layer of porous SiOCH low-k film on line capacitance and leakage current were investigated in the 80nm-pitch triple layer interconnect structure. The damage layer thickness was controlled from zero to 8nm by the RIE, wet process and Cu surface treatment. The damage layer thickness is defined by TEM-EELS analysis. The line capacitance and leakage current were increased by moisture uptake. The dielectric constant of damage layer including moisture was estimated 7.6 by the capacitance simulation. The moisture control of the damage layer in porous SiOCH low-k film is very important to reduce the line capacitance and improve the line leakage current as well as damage layer elimination.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Moisture Uptake Impact on Damage Layer of Porous Low-k Film in 80nm-Pitched Cu Interconnects

et al. 2011

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“…To suppress the damage of interlayer dielectric by the ashing process during the removal of the trench resist, the metal hard mask (MHM) process has been studied instead of the conventional resist mask process. [12][13][14][15][16][17][18][19][20][21][22][23][24] As a hard mask in the MHM process, Titanium nitride (TiN) has been investigated. [20][21][22][23][24][25][26][27][28][29][30][31] This is because the alignment pattern for photolithography can be easily recognized through TiN film compared to other metal films such as Tantalum nitride (TaN) film.…”

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confidence: 99%

High-Performance Metal Hard Mask Process Using Fiber-Textured TiN Film for Cu Interconnects

Torazawa

Harada

Konishi

et al. 2016

ECS J. Solid State Sci. Technol.

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One of the most challenging issues in the metal hard mask process for copper interconnects is controlling the residual stress in TiN mask. The relationship between the residual stress and the feature size of the trench was investigated using a mechanical simulation. It was found that the trench deformation at a specific pattern due to the residual compressive stress in TiN film resulted in void formation in Cu. To overcome this problem, the correlation between the residual stress and the film properties of TiN was investigated and a potential TiN mask in the metal hard mask process was studied. The residual stress in TiN film and the etching performance were correlated with the composition and the crystal structure of TiN. The grain growth was suppressed by reducing the energy of sputtered atoms during the deposition of TiN, resulting in low residual stress in TiN film with keeping the etching performance for TiN. By applying low stress TiN mask which had a fiber-textured structure, the trench deformation at a specific pattern could be suppressed and thus Cu filling was perfectly achieved. The metal hard mask process using TiN film which had a fiber-textured structure was demonstrated to be high performance. As the wiring pitches in copper (Cu) interconnect continue to become smaller, resistive-capacitive (RC) delay due to the increase in the capacitance between Cu lines becomes a critical problem. Therefore, the low k-value dielectric materials have been studied to reduce the capacitance between Cu lines.1-8 However, the low-k materials are known to be easily damaged by the post-processes such as the resist ashing process with oxygen (O 2 ) plasma 9-11 because of their low mechanical strength, and it results in k-value increasing.To suppress the damage of interlayer dielectric by the ashing process during the removal of the trench resist, the metal hard mask (MHM) process has been studied instead of the conventional resist mask process.12-24 As a hard mask in the MHM process, Titanium nitride (TiN) has been investigated. [20][21][22][23][24][25][26][27][28][29][30][31] This is because the alignment pattern for photolithography can be easily recognized through TiN film compared to other metal films such as Tantalum nitride (TaN) film. However, the serious problems occurred in the MHM process due to high residual stress in TiN mask. One of the problems is that the trench deformation after the etching process, which is known as the wiggling phenomenon.32 This is due to the stress relaxation of TiN film after the trench formation with the etching process, and it results in the buckled structure. Therefore, the approaches to reduce the residual stress in TiN film used as a hard mask have been also studied. One approach to reduce the residual stress is to reduce the thickness of TiN mask. However, thinner TiN mask tends to result in worse property of a hard mask in the self-aligned via process, and the shrink of the pitches between via and trench occurs. It results in degrading the device yield or the reliability per...

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Reliability comparison on self-aligned via and punch-through via etch methods of hard-mask based Cu/ultra low-k interconnects

Zhou

Gan

et al. 2013

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

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In this paper reliability performance of two all-in-one etch methods, self-aligned via (SAV) and punch-through (PT), has been investigated in detail. The breakdown voltage (Vbd) has been dramatically improved with the SAV etch method.However, electromigration (EM) performance has showed ~50% degradation. On the other hand, no degradation was found in stress migration (SM) performance. The underlying mechanisms for the reliability difference are detailed.

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Highly manufacturable ELK integration technology with metal hard mask process for high performance 32nm-node interconnect and beyond

Cited by 3 publications

References 0 publications

Moisture Uptake Impact on Damage Layer of Porous Low-k Film in 80nm-Pitched Cu Interconnects

Moisture Uptake Impact on Damage Layer of Porous Low-k Film in 80nm-Pitched Cu Interconnects

High-Performance Metal Hard Mask Process Using Fiber-Textured TiN Film for Cu Interconnects

Reliability comparison on self-aligned via and punch-through via etch methods of hard-mask based Cu/ultra low-k interconnects

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