Highly performant double gate MOSFET realized with SON process

Quantum short-channel compact model for the threshold voltage in double-gate MOSFETs with high-permittivitty gate dielectrics

“…8 shows also that the fit between the model and the numerical simulation is within ±15% even at gate lengths < 20 nm. Table 1 Comparison between V T extracted in different double-gate devices and V T calculated using the short-channel quantum analytical model Finally, the model was used to fit experimental V T Õs measured on long and short-channel symmetric DG MOSFETs [17,18] with different film thicknesses. Table 1 summarizes the geometrical parameters and the doping level of devices considered in this work.…”

3D nanowire gate-all-around transistors: Specific integration and electrical features

“…This discrete effective transistor width introduces some restrictions in complementary metal oxide semiconductor (CMOS) devices layout [4]. We proposed a fin Field Effect Transistor (fin-FET) -like process [5] combined with silicon-on-nothing (SON) technologies [6,7] to obtain a matrix of suspended stacked nanowires CMOS devices ( Figs. 1 and 2).…”

Investigation of Empty Space in Nanoscale Double Gate (ESDG) MOSFET for High Speed Digital Circuit Applications

“…The conventional drift-diffusion model of charge transport neglects the "non-local" effects such as velocity overshoot and impact ionization which are easily incorporated through the use of an EBT (which uses a higher order approximation of the Boltzmann transport equation) [8]. The reported off state current and sub-threshold slope were 1 nA/µm and 70mV/decade respectively [9] and further DG SON process offers very thin thickness channel with well controlled thickness (epi) and thus solve the major issues encountered during DG process integration. However, the DG SON architecture suffers from serious drawback i.e.…”