Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity

Chen, Y. S.; Lee, H. Y.; Chen, P. S.; Gu, Pei-Yi; Chen, C. W.; Lin, Wei‐Cheng; Liu, W. H.; Hsu, Yu‐I; Sheu, Shyh-Shyuan; Chiang, Pei-Chia; Chen, Wen Shan; Chen, F. T.; Lien, Chenhsin; Tsai, Ming-Jinn

doi:10.1109/iedm.2009.5424411

Cited by 187 publications

(107 citation statements)

References 4 publications

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“…The signals need to reach M1 or M2 from the memristor layer only when they access the pins of logic blocks. Moreover, as stated in Section I, the size of a memristor cell can be close to or even smaller than the width of a metal wire [9,10]. So memristors can easily fit into the design in Fig.…”

Section: A Basic Structurementioning

confidence: 99%

“…The current leading memristor technology for the time being has outperformed many other emerging NVMs in some important aspects and performs similar to them in the other aspects. It has been demonstrated that memristor is scalable below 30nm [9], can be fabricated with device size as small as F 2 (F is the feature size) with full compatibility of CMOS [10], and can be programmed within 5ns at 180nm technology node [11]. Due to the advantages of its device property over SRAM and other emerging NVMs, numerous research efforts have been made to adopt memristors for systemlevel integration [12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

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mrFPGA: A novel FPGA architecture with memristor-based reconfiguration

Cong

Xiao

2011

2011 IEEE/ACM International Symposium on Nanoscale Architectures

116

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Abstract-In this paper, we introduce a novel FPGA architecture with memristor-based reconfiguration (mrFPGA). The proposed architecture is based on the existing CMOS-compatible memristor fabrication process. The programmable interconnects of mrFPGA use only memristors and metal wires so that the interconnects can be fabricated over logic blocks, resulting in significant reduction of overall area and interconnect delay but without using a 3D diestacking process. Using memristors to build up the interconnects can also provide capacitance shielding from unused routing paths and reduce interconnect delay further. Moreover we propose an improved architecture that allows adaptive buffer insertion in interconnects to achieve more speedup. Compared to the fixed buffer pattern in conventional FPGAs, the positions of inserted buffers in mrFPGA are optimized on demand. A complete CAD flow is provided for mrFPGA, with an advanced P&R tool named mrVPR that was developed for mrFPGA. The tool can deal with the novel routing structure of mrFPGA, the memristor shielding effect, and the algorithm for optimal buffer insertion. We evaluate the area, performance and power consumption of mrFPGA based on the 20 largest MCNC benchmark circuits. Results show that mrFPGA achieves 5.18x area savings, 2.28x speedup and 1.63x power savings. Further improvement is expected with combination of 3D technologies and mrFPGA.

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Section: A Basic Structurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mrFPGA: A novel FPGA architecture with memristor-based reconfiguration

Cong

Xiao

2011

2011 IEEE/ACM International Symposium on Nanoscale Architectures

116

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“…The filament-type RRAM has demonstrated high switching speeds (of the order of GHz), large R On /R Off ratio (>10 7 ), low operation voltages (<1 V) and low switching currents (of the order of nanoamperes) [4,8,26]. However, its endurance, retention and uniformity performances have been facing great challenges [1,2].…”

Section: Performance Improvement Approaches To Filament-type Rrammentioning

confidence: 99%

“…As for VCM-based RRAM, the material of the buffer layer is usually oxidizable metal or metal oxide, such as Ti or TiO 2 , which is as thin as several nanometers [24][25][26]. The reason for using such a buffer layer is as follows: for this type of RRAM, the filament formation and rupture are associated with the distribution of movable oxygen ions and oxygen vacancies in the oxide films, and such an oxidizable buffer layer can be considered as the oxygen reservoir to help stabilize the local oxygen migration for the filament formation and rupture (the role is similar to that of the reactive metal electrode discussed previously).…”

Section: Interface Engineeringmentioning

confidence: 99%

Approaches for improving the performance of filament-type resistive switching memory

et al. 2011

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Resistive random access memory (RRAM) has received significant research interest because of its promising potential in terms of down-scaling, high density, high speed and low power. However, its endurance, retention and uniformity are still imperfect. In this article, the physical mechanisms of filament-type RRAM and the approaches for improving the switching performance, including doping, process optimization and interface engineering, are introduced. Many metal-oxide-metal systems show electrically induced resistive switching (RS) effects and have therefore been proposed as the basis for future non-volatile memories [1,2]. Resistive random access memory (RRAM) will also play an important role in the developing field of logic circuits, field programmable gate arrays and memristors [3]. Depending on where RS occurs, various proposed RS models can simply be classified in to two categories: the interface-type, which can be attributed to the modification of the interface barrier height; and the filament-type, which is cell size independent and only occurs in a localized active area. The filament-type RRAM is thought to be suitable for down-scaling to 20 nm and below [2]. However, the intrinsic mechanisms are still divergent and robust cycling endurance, data-retention and performance uniformity must be addressed for commercial applications. The key to improving filament-type RRAM is to effectively control and optimize the concentration and profile of inner mobile ions in the binary transition-metal-oxide (TMO) films. This article *Corresponding author (email: liuming@ime.ac.cn) introduces the approaches for improving the RS performances of filament-type RRAM, including material modifications and interface engineering.

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“…It is because the number of partially-connected CFs decreases in a pristine cell as initial defect density is reduced. Considering that the number of initial defects decreases with the reduction of cell volume, more uniform V foming distribution is expected in the case of a small-sized RRAM cell [19].…”

Section: Applicationsmentioning

confidence: 99%

A Finite Element Model for Bipolar Resistive Random Access Memory

Kim¹,

Lee²,

Lee³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The forming, reset and set operation of bipolar resistive random access memory (RRAM) have been predicted by using a finite element (FE) model which includes interface effects. To the best of our knowledge, our bipolar RRAM model is applicable to realistic cell structure optimization because our model is based on the FE method (FEM) unlike precedent models.Index Terms-Realistic cell structure optimization, finite element method (FEM), bipolar resistive random access memory (RRAM).

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Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity

Cited by 187 publications

References 4 publications

mrFPGA: A novel FPGA architecture with memristor-based reconfiguration

mrFPGA: A novel FPGA architecture with memristor-based reconfiguration

Approaches for improving the performance of filament-type resistive switching memory

A Finite Element Model for Bipolar Resistive Random Access Memory

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