Highly selective isotropic chemical dry etching for gate-all-around devices: nanosheet, forksheet and complementary FETs

Muraki, Y.; Oniki, Yusuke; Gowda, P. Puttarame; Altamirano-Sánchez, Efraín; Mertens, Hans; Horiguchi, N.; Holsteyns, Frank; Kal, S.; Alix, Cheryl; Kumar, Kaushik; Mosden, Aelan; Hurd, Trace; Takahashi, Nobuyuki

doi:10.1117/12.2613723

Cited by 2 publications

(3 citation statements)

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“…Unfortunately, the thicker top SiGe layer of the samples of Fig. 4 was etched faster than the two bottom layers due to a microloading effect 23 (see, e.g., inset of Fig. 5).…”

Section: Measurement Of Sige Volume Of Full-loop Forksheet Samplesmentioning

confidence: 99%

Model-free measurement of lateral recess in gate-all-around transistors with micro hard-X-ray fluorescence

Bogdanowicz

Oniki

Kenis

et al. 2023

J. Micro/Nanopattern. Mats. Metro.

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The processing of gate-all-around (GAA) Si transistors requires several isolated and vertically stacked nanometer-thick Si sheets or wires. For this purpose, the sacrificial SiGe layers of a SiGe/Si superlattice are etched selectively and laterally. Controlling the quantity of etched SiGe material, i.e., the so-called SiGe cavity depth, is critical for optimal device performance. Unfortunately, this critical dimension can only be measured by time-consuming cross-sectional transmission electron microscopy (TEM), which results in limited statistics and hence insufficient control of the cavity depth across wafers and batches. This paper evaluates the capabilities of micro hard x-ray fluorescence (μHXRF) for the determination of cavity depth as a fast and non-destructive alternative to TEM. As we show, μHXRF provides cavity depth values in excellent agreement with TEM. In addition, two critical advantages of the technique demonstrated here are that, thanks to the very high energy of the incoming and emitted X-rays, the SiGe volume is extracted without requiring any complex model and without any correlation to other geometrical parameters of the complex GAA device.

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“…Unfortunately, the thicker top SiGe layer of the samples of Fig. 4 was etched faster than the two bottom layers due to a microloading effect 23 (see, e.g., inset of Fig. 5).…”

Section: Measurement Of Sige Volume Of Full-loop Forksheet Samplesmentioning

confidence: 99%

Model-free measurement of lateral recess in gate-all-around transistors with micro hard-X-ray fluorescence

Bogdanowicz

Oniki

Kenis

et al. 2023

J. Micro/Nanopattern. Mats. Metro.

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“…Owing to the very small dimensions (e.g., sub-10 nm nanowire channel diameter), high etching selectivity towards both Si1-xGex and Si, and excellent process controls are mandatory. This sets stringent requirements on the epitaxial stacks (thicknesses and composition control, sharpness of interfaces, and absence of strain relaxation) (4) as well as on the etch process itself (high selectivity, limited Si1-xGex and Si consumption) (5)(6)(7).…”

Section: Introductionmentioning

confidence: 99%

“…The selective removal of Si1-yGey requires a great precision in its adjustment, with the risk of experiencing process variabilities and yield issues. Selective SiGe etching is typically done in advanced wet or dry chemistries and is sensitive to both strain in and oxidation of individual layers (4)(5)(6). Also, HCl-based vapor etching has been reported for Corresponding author: roger.loo@imec.be SiGe removal, with high selectivity towards Si (7).…”

Section: Introductionmentioning

confidence: 99%

(Digital Presentation) Selective SiGe Vapor Etching Using Br₂ in View of Nanosheet Device Isolation

Loo¹,

Gosset²,

Isaji³

et al. 2022

ECS Trans.

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Both forksheet and CFET device layouts contain local dielectric isolation layers to circumvent junction isolation trade-offs which are specific for these designs. Typical fabrication schemes start with the epitaxial growth of complicated SiGe/Si multi stacks with at least two different Ge concentrations where a Ge-rich SiGe layer is later replaced by an isolating dielectric. This work proposes a low temperature Br2-based vapor etching process as an option for the selective SiGe removal in the isolation fabrication. After initial process screening on blanket epi layers to compare etching behavior for different process gases as function of material composition and crystallinity, it is demonstrated on patterned test structures that Br2 etching enables high etching selectivity of Si0.5Ge0.5 towards Si and Si1-xGex (x = 0.2 - 0.3).

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Highly selective isotropic chemical dry etching for gate-all-around devices: nanosheet, forksheet and complementary FETs

Cited by 2 publications

References 0 publications

Model-free measurement of lateral recess in gate-all-around transistors with micro hard-X-ray fluorescence

Model-free measurement of lateral recess in gate-all-around transistors with micro hard-X-ray fluorescence

(Digital Presentation) Selective SiGe Vapor Etching Using Br₂ in View of Nanosheet Device Isolation

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Highly selective isotropic chemical dry etching for gate-all-around devices: nanosheet, forksheet and complementary FETs

Cited by 2 publications

References 0 publications

Model-free measurement of lateral recess in gate-all-around transistors with micro hard-X-ray fluorescence

Model-free measurement of lateral recess in gate-all-around transistors with micro hard-X-ray fluorescence

(Digital Presentation) Selective SiGe Vapor Etching Using Br2 in View of Nanosheet Device Isolation

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(Digital Presentation) Selective SiGe Vapor Etching Using Br₂ in View of Nanosheet Device Isolation