VLSI reliability issues such as hot-carrier effects, dielectrics and metallization, are reviewed and discussed. VLSE have been developed mainly with continued reliability in mind. However, a new challenging approach to VLSI reliability is now greatly needed in response to the 'paradigm shift' now being brought about by simple scaling limitations, increased process complexity and VLSI application to advanced systems. A good example of this shift is the new movement from simple failure analysis by sampling the output of a manufacturing line to the 'building-in-reliability' approach. To pursue this technique, greater importance will be attached to a deeper physical understanding (including frequent use of CAD/DA) of the significant relationships between the input variables and product reliability, and to total concurrent engineering from research labs to production sites. Furthermore, fast new VLSI testing methods and new yield-enhancing redundancy techniques, resulting in cost reduction, will be increasingly needed to achieve high reliability for VLSIS with IO9 devices on a single chip. This review aims at understanding the physics underlying important reliability problems: hot-carrier effects in scaled MOSWTS, dielectrics in the insulator and electro/stress migration in the interconnection.