IEEE International Electron Devices Meeting 2003
DOI: 10.1109/iedm.2003.1269352
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How far will silicon nanocrystals push the scaling limits of NVMs technologies?

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Cited by 70 publications
(64 citation statements)
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“…Note that despite numerous TEM (Transmission Electron Microscopy) analyses, the exact crystalline nature of the NDs could not be determined due to their nanometric size [25]. But all high resolution TEM of NDs deposited between 570 and 650 • C, show that NDs are crystalline [26]. This range of temperature was that of our whole runs.…”
Section: Operating Conditions Tested and Experimental Resultsmentioning
confidence: 97%
“…Note that despite numerous TEM (Transmission Electron Microscopy) analyses, the exact crystalline nature of the NDs could not be determined due to their nanometric size [25]. But all high resolution TEM of NDs deposited between 570 and 650 • C, show that NDs are crystalline [26]. This range of temperature was that of our whole runs.…”
Section: Operating Conditions Tested and Experimental Resultsmentioning
confidence: 97%
“…According to our simulation process, these phenomena can be attributed to the fact that Young's modulus of Au is larger than that of Ag and Young's modulus for both Au and Ag is larger than that of SiO 2, but smaller than that of Al 2 O 3 . Recently, Campera et al [20] modelled the experimental data of De Salvo et al [21] and concluded that electrons are stored in defects in the nanocrystals/oxide interface. Our previous research has also demonstrated that the defects associated with the strained GaAs nanoparticles interfaces can capture charges and serve as charge storage centres, causing improvement in charge storage performance [3].…”
Section: Resultsmentioning
confidence: 99%
“…In the field of non-volatile memory devices (NVM), replacing the traditional floating gate by silicon nanocrystals is a promising way to push the downscaling of these devices toward sub-100 nm technological nodes [1,3]. Using this technique, high density silicon nanocrystals, up to 10 12 cm À2 , are required to achieve a sufficient programming window and reduce electrical fluctuation from one device to the other [1,4,5].…”
Section: Introductionmentioning
confidence: 99%
“…Using this technique, high density silicon nanocrystals, up to 10 12 cm À2 , are required to achieve a sufficient programming window and reduce electrical fluctuation from one device to the other [1,4,5]. Recent papers have shown that using metallic dots can easily provide high-density 2D-arrays and maintain compatibility with standard CMOS technology [6,8].…”
Section: Introductionmentioning
confidence: 99%