Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing

Abstract

A novel high-speed sense amplifier for ultra-lowvoltage SRAM applications is presented. It introduces a completely different way of sizing the aspect ratio of the transistors on the data-path, hence realizing a current-voltage hybrid mode Sense Amplifier. Extensive post-layout simulations have proved that the new Sense Amplifier provides both high-speed and low-power properties, with its delay and power reduced to 25.8% and 37.6% of those of the best prior art. It also offers a much better read-effectiveness and robustness against the bit-and data-line capacitances as well as V DD variations. Furthermore, the new Sense Amplifier is able to tolerate a large difference between the parasitic capacitances associated with the complementary DLs. It can operate down to a supply voltage of 0.9 V, the lowest reported for a 0.18 m CMOS process. A modified cross-coupled amplifier is also introduced, allowing the Sense Amplifier to operate down to 0.55 V.Index Terms-Low-power SRAM, low-voltage SRAM, sense amplifier (SA).

A Reliable, Process-Sensitive-Tolerant Hybrid Sense Amplifier for Ultralow Power SRAM

“…7 and Fig. 8 Compare technique [10] can operate lower down up to 0.9V and proposed design can work up to near threshold 0.6V as shown in Fig. 6.…”

“…However, latch type SA's are vulnerable to sensing failure, which is referred to as the parametric failure caused by malfunction of the sense amplifier due to insufficient sensing margin against the input offset voltage [11]. (2) Voltage/current mode sense amplifier [10]. The parasitic resistance of a metal or poly silicon line has a significant influence on the signal propagation delay over the interconnect line from local to global sensing stage, this increase the sensing delay.…”

“…This in turn affects sense amplifier reliability [9]. This paper is organize as follows section II discusses the conventional voltage latch sense amplifier, Voltage/current mode SA [10] and proposed design. Section III describes the designed work and its operation.…”

Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity

“…Cascodecurrent-load CSAs (CCL-CSAs), [24][25], require long BL settling times and have a small 1st-stage voltage difference when reading a small cell current (I CELL ). Hybrid SAs [26][27] have small differential voltage on the data-lines (DLs) when reading a small I CELL . Current-mirror CSA (CM-CSA) [28][29] has fast read speed but cannot sense small I CELL , due to mismatch in the mirror-stage device.…”

“…Since all of these SA designs utilize the differential output current of the current conveyor, their improvement is only incremental. Reference [26] clearly indicates that the differential current is equal to the current flowing into the cell node where a "0" is stored, i.e., I CELL .…”