Abstract:lhis paper presents a new method for detecting defect and fabrication variations in both digital and analog CMOS circuits by simultaneously puking the power supply raik and analyzing the temporal andlor the spectral characteristics of the resulting transient rail currents. lhe method presented has a distinct advantage over other forms of iDD testing because it requires a single test vector to excite and expose the presence of a defect or irregular fabrication process condition. lhis paper presents data fhom si… Show more
“…Nontarget tests, such as at-speed Boolean methods, are the only tests available. Other tests, such as the transient power supply current test, i,l,x, require further research to describe their capabilities [74,75].…”
The IC test industry has struggled .for more than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS ICs that uses defect classes based on measured defect electrilxd properti'es. Defect classes differ from traditional fault models. Our defect class approach requires that the test strategy match the defect electrical properties, while fault models require that IC defects match the fault definition. We use data from Sandia Labs failure analysis and lest facilities and from public literature [l-601. We describe test pattern requirements for each defect class and propose a test paradigm.
“…Nontarget tests, such as at-speed Boolean methods, are the only tests available. Other tests, such as the transient power supply current test, i,l,x, require further research to describe their capabilities [74,75].…”
The IC test industry has struggled .for more than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS ICs that uses defect classes based on measured defect electrilxd properti'es. Defect classes differ from traditional fault models. Our defect class approach requires that the test strategy match the defect electrical properties, while fault models require that IC defects match the fault definition. We use data from Sandia Labs failure analysis and lest facilities and from public literature [l-601. We describe test pattern requirements for each defect class and propose a test paradigm.
“…This method provides a high fault coverage at a lower testing cost. Similar techniques have been proposed for mixedsignal circuits, [7], [8]. These methods involve monitoring the power supply current (IDD) waveform of the circuit under test (CUT) and comparing it with the waveform produced by the fault-free circuit.…”
This paper describes the comparison of input stimuli as a means of testing mixed-signal circuits. Current testing that measures the integral of the power supply current in the time-domain is used to detect faults. The main objective is to achieve real-time testing in which there is no need to analyze the results of testing. Simulation results show that a step-voltage input stimulus is effective for detection of bridging and breaking faults in an A/D converter. Since this input signal allows the current to be measured at discrete time intervals, it is applicable for realtime current testing and can be used for built-in test and production test.
“…It appeared [6] that our method could detect faults that are undetected by IDDQ testing, such as stuck-open faults [3]. Moreover, IDDQ testing is limited to technologies with zero or very small quiescent currents [4]. As it is explained later, the applicability of our method should not be limited only to these technologies.…”
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confidence: 98%
“…Our method is different since only a small part (DC and first harmonic) of the frequency spectrum is estimated using a simple FFT on a few current samples. Beasley et al [4] presented a method which pulses VDD and GND signals while the inputs are siet t o a fixed bias voltage. In their paper, they showed that the supply current frequency spectrum of a defective circuit varied a defect-free circuit without proposing any method t o used this information.…”
mentioning
confidence: 99%
“…In their paper, they showed that the supply current frequency spectrum of a defective circuit varied a defect-free circuit without proposing any method t o used this information. However, the fact that the entire circuit is stimulated makes single defects less obvious [4]. Moreover it requires simulations of the entire circuit in order to get reference results, which becomes untractable for large VLSI IC's.…”
In this paper, we explore the potential of FFTs in digital IC tests. The effects of three parasite contact types are investigated. Results show that unappropriate logical values on output voltages are easily detected and that FFTs on supply current can make detectable undesired contacts causing additional delays. Application of the method to technologies with non small quiescent currents and to large ICs is also discussed.
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