IC Piracy prevention via Design Withholding and Entanglement

Abstract

Globalization of the semiconductor industry has raised serious concerns about trustworthy hardware. Particularly, an untrusted manufacturer can steal the information of a design (Reverse Engineering), and/or produce extra chips illegally (IC Piracy). Among many candidates that address these attacks, Design Withholding techniques work by replacing a part of the design with a reconfigurable block on chip, so that none of the manufactured chips will function properly until they are activated in a trusted facility, where the withheld function is restored back into the reconfigurable block on chip. However, most existing approaches are ad-hoc based, and are facing two major challenges: 1) susceptibility to a category of algorithmic attacks, from attackers in a strong position, such as a manufacturer; and 2) scaling up the defense level is checkmated by the explosion of hardware cost that has to be paid at the designer's side. In this paper, we propose a novel protection scheme, called Entanglement, which can substantially strengthen the Design Withholding framework: 1) the algorithmic attacks are prevented by forcing the attacker to solve a huge number of problems of high computational complexity; 2) the attack cost (in terms of computational complexity) is quantitatively controllable at the designer's end, with low hardware overhead: while the cost of attack can be increased exponentially, the hardware overhead imposed on the designer's side grows only linearly. The proposed work distinguishes itself from the previous works by not relying on the difficulty of finding the solution for some NP-Complete/NP-Hard problems, but rather, on the exponentially boosted number of such problems that an attacker has to solve, while carefully maintaining the growth of the hardware overhead to be scalable via Entanglement.978-1-4799-7792-5/15/$31.00

Generalized SAT-Attack-Resistant Logic Locking

“…3(a). Two symmetric groups of cells in the K-map always have the same binary distance structure defined in (12). One example of the group of cells that is symmetric to those for the Lf T in Fig.…”

“…The f and g in our design can be complementary as well. Select Lg T = [0, 1, 2, 3, 4, 5, 7] and Lf T = [6,8,9,10,11,12,13,14,15]. It can be found that Lf T i = 5 and Lg T j = 6 satisfy Constraint 1.…”

“…Example 3 Constrain 1 is not sufficient to guarantee the existence of correct keys. For example, take Lf T = [0, 1, 3, 2] and Lg T = [0, 4,12,8]. Constraint 1 is also satisfied by taking…”

“…Many logic locking schemes have been developed previously by inserting XOR/XNOR gates [7]- [9], MUX gates [10], [11], or look-up tables (LUTs) [12], [13] controlled by keys. However, these designs can be easily decrypted by the satisfiability (SAT)-based attack [14], which uses Boolean SAT solvers to iteratively update and solve the conjunctive normal form (CNF) formula of the target circuit.…”

Key Generation for Hardware Obfuscation Using Strong PUFs

“…Scrambling the interconnection network in a permutation-based technique will cause the circuit to only work with a correct key which will configure the interconnection network [10]. Other work has hidden parts of the circuit in a configurable lookup table (LUT) [11]. With those obfuscation methods, the effort for an attacker to find the correct key will become computationally infeasible [12].…”