Identifying redundant path delay faults in sequential circuits

Tekumalla, R.C.; Menon, P.R.

doi:10.1109/icvd.1996.489643

Cited by 22 publications

(7 citation statements)

References 8 publications

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“…In general, such false paths can be unintentionally created during the design flow, and it is important to find and exclude them from the circuit because they can make a negative impact on some aspects of circuit design. Several methods have been proposed to identify false paths in a combinational circuit or a sequential circuit at gate level (GL) [2], [3], [4], [5], [6]. At register transfer level (RTL) or higher level, on the other hand, false paths can be also identified by analyzing high-level design information (e.g., structural information, data flow, control flow, etc.)…”

Section: Introductionmentioning

confidence: 99%

Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool

Iwagaki

Takehiro

Ichihara

et al. 2012

2012 IEEE Asia Pacific Conference on Circuits and Systems

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This paper presents a circuit optimization flow with a logic synthesis tool in a situation where register transfer level (RTL) false paths are given. RTL false path information can be utilized to obtain a more optimized circuit in logic synthesis. It is important to consider which RTL false paths are useful in logic synthesis so that an optimized circuit can be synthesized efficiently. The characteristics of such effective RTL false paths are analyzed from synthesis results in preliminary experiments. On the basis of the analysis, this paper formulates the problem of selecting RTL false paths and proposes a solution for it. Experimental results show that the proposed false path selection algorithm is effective in reducing area, delay and synthesis time compared with several possible false path selection methods.Index Terms-Logic synthesis, register transfer level false path, false path selection, area and delay optimization.

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Section: Introductionmentioning

confidence: 99%

Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool

Iwagaki

Takehiro

Ichihara

et al. 2012

2012 IEEE Asia Pacific Conference on Circuits and Systems

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show abstract

“…Several false path identification methods at the gate level for combinational circuits [1]- [3] and for sequential circuits [4], [5] have been proposed. However, since it is difficult to apply false path identification methods at the gate level for large circuits containing a tremendous number of paths, some methods using register transfer level (RTL) design information, instead of gate level, have been proposed [6]- [8].…”

Section: Introductionmentioning

confidence: 99%

A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification

Iwata

Ohtake

Fujiwara

2010

IEICE Trans. Inf. & Syst.

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SUMMARYInformation on false paths in a circuit is useful for design and testing. The use of this information may contribute not only to reducing circuit area, the time required for logic synthesis, test generation and test application of the circuit, but also to alleviating over-testing. Since identification of the false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, giving restriction on logic synthesis is the only way to establish the correspondence. However, it is not practical for industrial designs. In this paper, we propose a method for mapping RTL false paths to their corresponding gate level paths without such a specific logic synthesis; it guarantees that the corresponding gate level paths are false. Experimental results show that our path mapping method can establish the correspondences of RTL false paths and many gate level false paths. key words: false path, high level testing, path mapping, functional equivalence

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“…Even if scan dwign is used, the ofly fatits that can affect circuit behavior me those that are sensitized during normrd (nonscan) operation. We identification of redundant and untestable fadts [20,21] can be used to rduce test generation effort, the remaining set wodd stiUcontain fatits that need not be testd.~us, primitive fadts must be identified assuming non-scan operation to avoid unnecessary tests and pessimistic twt restits. me god of this paper is to develop methods of identifying primitive fardts in non-scan squentid tircuits, and deriving robust tests for robusfly testable primitive fadts.…”

Section: Introductionmentioning

confidence: 99%

On primitive fault test generation in non-scan sequential circuits

Tekumalla

Menon

1998

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '98

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A method is presented for identifying primitive path-delay faults in non-scan sequential cixuits and generating robwt tests for all robustly testable primitive faults. It uses the concept of sensitizing cubes introduced in an earlier paper and a nw, more eficient algon.thmfor generating them. Sensitizing cubes of the natstate and output logic are used to obtain static sensitizing vectors that can be applied to the non-scan sequential cixuit as part of a vector-paiz These vector-pairs are also used in den.ving robust tests. Initializing sequencesfim a reset state and sequences that propagate fault effects~m @p-@ps to pn.nra~outputs are also generated The proposed method has been implemented and used to derive testsforprimitivefaults in ISCAS'89 and MCNC'91 benchmark cixuits.

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Identifying redundant path delay faults in sequential circuits

Cited by 22 publications

References 8 publications

Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool

Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool

A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification

On primitive fault test generation in non-scan sequential circuits

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