Impact of fin width on digital and analog performances of n-FinFETs

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

“…However, according to ref. [22], the measured V EA can differ from the intrinsic device Early voltage (V A ) due to the influence of the series resistance and carrier mobility as given in Eq. (4):…”

Experimental characterization of the subthreshold leakage current in triple-gate FinFETs

“…The performance of these transistors is expected to be severely degraded by short-channel effects (SCEs). For sub-100 nm scaling of MOSFETs, triple-gate field-effect transistors like FinFETs have attracted considerable attention due to their immunity to SCEs and proximity to standard bulk planar CMOS processing [2][3][4][5][6][7]. Since the advanced triple-gate FinFETs require ultra-thin gate dielectrics, gate tunneling currents may affect the drain leakage current in the subthreshold region of operation, leading to a substantial increase of the leakage energy which is harmful for applications in circuits of low power consumption.…”

A novel nanoscale fin field effect transistor by amended channel: Investigation and fundamental physics

“…The variation of threshold voltage with temperature is related to the height and width of fins [6,21]. Narrower fins lead to higher threshold voltage [6,22]. In the ACFinFET, the flat part of the fin has narrower width; so, the threshold voltage becomes higher in relation to the C-FinFET.…”