Impact of HfO2 buffer layers on data retention characteristics of ferroelectric-gate field-effect transistors

Aizawa, Katsuo; Park, Byung–Eun; Kawashima, Yoshihito; Takahashi, Kazuhiro; Ishiwara, Hiroshi

doi:10.1063/1.1806274

Cited by 108 publications

(68 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Its functionality arises from the attenuation of the charge carrier concentration in the semiconductor by the ferroelectric polarization of the gate insulator. Even though inorganic FeFETs have been studied for decades, a memory performance of any practical value has been achieved only in recent years [2][3][4][5][6][7][8] . The main problems that have arisen are charge trapping at the ferroelectric-semiconductor interface and the lack of thermal stability of the interface.…”

mentioning

confidence: 99%

High-performance solution-processed polymer ferroelectric field-effect transistors

et al. 2005

View full text Add to dashboard Cite

We demonstrate a rewritable, non-volatile memory device with fl exible plastic active layers deposited from solution. The memory device is a ferroelectric fi eld-effect transistor (FeFET) made with a ferroelectric fl uoropolymer and a bisalkoxy-substituted poly(p-phenylene vinylene) semiconductor material. The on-and off-state drain currents differ by several orders of magnitude, and have a long retention time, a high programming cycle endurance and short programming time. The remanent semiconductor surface charge density in the on-state has a high value of 18 mC m -2 , which explains the large on/off ratio. Application of a moderate gate fi eld raises the surface charge to 26 mC m -2 , which is of a magnitude that is very diffi cult to obtain with conventional FETs because they are limited by dielectric breakdown of the gate insulator. In this way, the present ferroelectricsemiconductor interface extends the attainable fi eldeffect band bending in organic semiconductors.A memory element based on the ferroelectric fi eld-effect transistor (FeFET) is attractive because of its non-volatile data retention, small size, rewritability, non-destructive read-out, low-voltage operation and short programming time 1 . Its functionality arises from the attenuation of the charge carrier concentration in the semiconductor by the ferroelectric polarization of the gate insulator. Even though inorganic FeFETs have been studied for decades, a memory performance of any practical value has been achieved only in recent years [2][3][4][5][6][7][8] . The main problems that have arisen are charge trapping at the ferroelectric-semiconductor interface and the lack of thermal stability of the interface. This has prompted the use of insulating buffer layers between the semiconductor and ferroelectric to prevent charge injection and protect the semiconductor from the high-temperature annealing procedure that is required for inorganic ferroelectrics. Crucial device parameters for all memory devices are the on/ off ratio, data retention time, programming cycle endurance and programming time. Current state-of-the-art inorganic FeFETs have on/off ratios up to 10 9 , a retention time of 16 days and a programming time of 10 -8 s (refs 5,8). This is promising, although the high production cost of this non-CMOS (complementary metal-oxide-semiconductor) technology may hinder widespread application.Organic fi eld-effect transistors are ideally suited for low-cost, low-performance logic circuit applications on fl exible substrates 9 .

show abstract

mentioning

confidence: 99%

High-performance solution-processed polymer ferroelectric field-effect transistors

et al. 2005

View full text Add to dashboard Cite

show abstract

“…More recently in the field of MFISFETs (metal-ferroelectric-insulator-semiconductor fieldeffect transistors) strong results have been presented by Takahashi et al [2005], and Aizawa et al [2004]. They investigated the Pt/SrBi 2 Ta 2 O 9 (SBT)/HfO 2 /Si structure and at the same time a Pt/(BiLa) 4 Ti 3 O 12 (BLT)/HfO 2 /Si structure.…”

Section: Ferroelectric/silicon Transistormentioning

confidence: 97%

“…As mentioned in section 2.5.1, HfO 2 was successfully used as a buffer layer for SBT/HfO 2 /Si and BLT/HfO 2 /Si FeFETs by Takahashi et al [2005], and Aizawa et al [2004]. The HfO 2 was annealed in oxygen at 800…”

Section: Survival Of 2degmentioning

confidence: 99%

“…Takahashi et al [2005], and Aizawa et al [2004] have used HfO 2 as a inter-diffusion barrier layer for silicon semiconductor substrates before the deposition of the ferroelectric gates SrBi 2 Ta 2 O 9 and (BiLa) 4 Ti 3 O 12 . The initial idea standing behind the development of the HfO 2 deposition process was also to use it as a buffer layer for limiting the diffusion between the ferroelectric, PZT, and AlGaN layers.…”

Section: Hfo 2 Buffer Layermentioning

confidence: 99%

See 1 more Smart Citation

Ferroelectric Gate on AlGaN/GaN Heterostructures

Malin¹,

Stolichnov²,

Muralt³

et al. 2006

2006 IEEE International Symposium on the Applications of Ferroelectrics

View full text Add to dashboard Cite

The capability of switching the spontaneous polarisation under an applied electric field in ferroelectric materials can be exploited for the use in low power, non-volatile, re-writable memory devices. Currently available commercially is ferroelectric random access memory, FeRAM, which allows for high speed, low voltage and greater write-erase endurance compared to its two main competitors, Flash and EEPROM, when using the one transistorone capacitor configuration. However, it is desired to further optimise the configuration in order to obtain better densification, faster access time and better reliability. One way to do such is to pass from the ferroelectric capacitors and develop ferroelectric field effect transistors.Exploiting the phenomenon of ferroelectricity and integrating ferroelectrics with the semiconductor technology has not been simple. The FeFET has been demonstrated using a silicon-based transistor, however commercial devices are not available. Challenges arise mainly due to the high temperature deposition of perovskite ferroelectrics causing the degradation of the ferroelectric/semiconductor interface due to inter-diffusion. Acquiring long term retention of the transistor behavior has also been problematic due to phenomenons such as charge injection and depolarisation.In this thesis a new approach to the problem of semiconductor devices with a ferroelectric gate is explored. Instead of using a silicon-based device, semiconductor heterostructures are investigated. Combining the high mobility channel existing in semiconductor heterostructures, with the non-volatile switching of the polarisation in the ferroelectric gate can pave the way to novel future devices.The AlGaN/GaN semiconductor heterostructure was chosen for two main reasons. The first is a two dimensional electron gas, 2DEG, located at the AlGaN/GaN interface which possesses better transport properties than a single layered semiconductor. Secondly, GaN and its alloys are known to have large chemical and temperature stability making them ideal to withstand the high temperature deposition process of perovskite ferroelectrics.The deposition of two ferroelectric layers onto the AlGaN heterostructure were investigated. Lead zirconium titanate, PZT, a traditional perovskite ferroelectric deposited at high temperature, was chosen for its high remanent polarisation and low coercive field. An alternative ferroelectric gate, the co-polymer poly(vinylidene fluoride/trifluoroethylene), P(VDF/TrFE)(70:30) was deposited and of interest due its low crystallisation temperature and low dielectric constant. Its remanent polarisation is smaller and coercive field larger than that of PZT, but were determined sufficient to observe the depletion effect in the two dimensional electron gas.The goals accomplished in this research were:Development of Ferroelectric Gate Processing: Deposition processes of the ferroelectric layers were developed and optimised in order to obtain a high quality ferroelectric, while maintaining the original transport properties...

show abstract

“…As mentioned above, the single-transistor-cell-type memory transistors composed of a ferroelectric gate insulator (GI) have been extensively investigated for the conventional Si electronics so far, in which various oxide ferroelectric materials such as Pb(Zr,Ti)O 3 (Shih W. C. et al, 2007;Tokumitsu et al, 1997), SrBi 2 Ta 2 O 9 (Horiuchi et al, 2010;Tokumitsu et al, 1999;Yoon S. M. et al, 1999), (Bi,La) 4 Ti 3 O 12 (Aizawa K. et al, 2004;Lee N. Y. et al, 2003), PbGeO 3 (Li T. et al, 2003), YMnO 3 (Ito D. et al, 2003), LiNbO 3 (Kim K. H., 1998), and BiFeO 3 (Lin C. et al, 2009) have been chosen as the ferroelectric GI. However, in realizing the plastic nonvolatile memory array, the use of oxide ferroelectric GI is absolutely unfavorable owing to the high crystallization temperature which is typically higher than 650 C. The overall process temperature should be suppressed below 200 C. Although some encouraging reports on the novel transfer technique (Roh J. et al, 2010) and ultra-low temperature process (Li J. et al, 2010) for the oxide ferroelectric thin films have recently been published, to secure the high-quality oxide ferroelectric GI for the memory transistor with low temperature process is still very challenging.…”

Section: Flexible Ferroelectric Memorymentioning

confidence: 99%