In this paper, we present complementary tunneling field effect transistors (CTFETs) based on strained Si with gate all around nanowire (GAA NW) structures on a single chip. The main focus is to suppress the ambipolar behavior of the TFETs with a gate-drain underlap. Detailed device characterization as well as demonstration of a CTFET inverter show that the ambipolar current is successfully eliminated for both p-and ndevices. The CTFET inverter transfer characteristics indicate maximum separation of the high/low level with a sharp transition (high voltage gain) at a Vdd down to 0.4V. Additionally, high noise margin levels of 40% of the applied Vdd are obtained. Index Terms-Silicon nanowire, tunneling FET, ambipolar behavior, inverter, CTFET