Impact of varying carbon concentration in SiC S/D asymmetric dual-k spacer for high performance and reliable FinFET

Abstract

We propose a reliable asymmetric dual-k spacer with SiC source/drain (S/D) pocket as a stressor for a Si channel. This enhances the device performance in terms of electron mobility (eMobility), current driving capabilities, transconductance (Gm) and subthreshold slope (SS). The improved performance is an amalgamation of longitudinal tensile stress along the channel and reduced series resistance. We analysed the variation in drive current for different values of carbon (C) mole fraction y in Si1−yCy. It is found that the mole fraction also helps to improve device lifetime, performance enhancement also pointed by transconductance variation with the gate length. All the simulations are performed in the 3-D Sentaurus TCAD tool. The proposed device structure achieved ION = 2.17 mA/μm for Si0.3C0.7 and found that Si0.5C0.5 is more suitable for the perspective of a process variation effect for 14 nm as the gate length. We introduce reliability issues and their solutions for Si1−yCy FinFET for the first time.

Homoepitaxial Growth on Si-Face (0001) On-Axis 4H-SiC Substrates

“…Silicon carbide (SiC) has been identified as the choice of material to fabricate high temperature, high voltage, high frequency, high power, radiation resistant devices due to its excellent physical and chemical properties [1][2][3]. General epitaxial growth is performed on off-axis 4H-SiC(0001) substrates, which would raise the cost of materials and devices, reduce the performance and reliability of the device because of the basal plane dislocations reproduction [4,5]. Homogeneous epitaxial growth using on-axis SiC substrate is helpful to solve these problems [6,7].…”