Impacts of a polycrystalline-silicon buffer layer on the performance and reliability of strained n-channel metal-oxide-semiconductor field-effect transistors with SiN capping

Abstract

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Impacts of SiN deposition parameters on n-channel metal-oxide-semiconductor field-effect-transistors

“…Channel strain engineering using highly tensile SiN capping has been popularly applied to modern technology to enhance the driving current of NMOS [1][2][3][4][5][6][7][8][9]. Based on the results presented in the present study, the N content and the Si-H bonds contained in the capping layer must be carefully controlled.…”

“…3) would release extra H species to the device and form new Si-H bonds at the Si/channel interface [10,14]. The breaking of Si-H bonds at the Si/channel interface during stressing is believed to be one of the major root causes responsible for the hot-carrier degradation [6][7][8]17]. These passivated Si-H bonds act as precursors to hot-carrier degradation [18,19] and are more easily broken during subsequent stressing [17].…”

“…Recently, the insertion of an ultra-thin buffer layer between the SiN capping layer and the underlying poly-Si gate electrode was demonstrated to effectively suppress the hydrogen diffusion and restore the reliability without compromising the device performance [7,8]. In this work, another effective approach to directly adjust the composition of SiN film by varying the precursor gas flow rate and deposition temperature is explored.…”

“…Channel strain engineering such as embedded SiC source/drain (S/D) [1,2] and highly tensile SiN capping layer [1][2][3][4][5][6][7][8][9] for n-channel metal-oxide-semiconductor field-effect-transistors (NMOSFETs) mobility enhancement has been pursued aggressively in scaled complementary metal-oxide-semiconductor (CMOS) devices. Among these methods, SiN capping technique has received much attention because it is easily implemented in modern ULSI technology.…”

Electrical Characteristics of the Uniaxial-Strained nMOSFET with a Fluorinated HfO2/SiON Gate Stack

“…However, a large amount of hydrogen during SiN CESL deposition would diffuse into the gate stacks to from Si-H/Hf-H bonds. The binding energy of the Si-H/Hf-H bonds is too small to resist subsequent channel hot electron stress (CHES) or constant voltage stress (CVS), which results in a considerable threshold voltage ( V TH ) shift and reliability degradation for the SiN CESL uniaxial-strained MOSFETs [ 21 , 22 ].…”