Implementation of an LDPC decoder on a heterogeneous FPGA-CPU platform using SDSoC

Roh, Si-Dong; Cho, Keol; Chung, Ki-Seok

doi:10.1109/tencon.2016.7848497

Cited by 7 publications

(1 citation statement)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Gallagher presented the SPA as the basic decoding technique in 1962. When it comes to realtime implementations like FPGAs (Roh et al, 2016;Ceroici, and Vincent, 2014), the SPA in (Mooij, Joris M., and Hilbert, 2005;Chen, et al, 2004) provide further addition and multiplication steps that render the computation complex.…”

Section: Introductionmentioning

confidence: 99%

Reducing LDPC Decoder Complexity by Using Fpga Based on Min Sum Algorithm

Kadhim

Korkmaz

2022

KJE

View full text Add to dashboard Cite

For double fields and large code lengths, Low-Density Parity-Check (LDPC) code approaches Shannon-limit execution. The goal of this project is to present an LDPC calculation for Min Sum (MS) decoding and equipment execution inquiry within a communication framework that has been proposed. The MS calculation principally utilizes the base and expansion finding procedure. The quantity of increases is subsequently altogether diminished, which tends to decrease the execution intricacy. The consequences of the reenactment show that the proposed MS interpreting calculation performs the same as the translating of the Sum-Product Algorithm (SPA) while keeping up with the principle highlights of the MS disentangling. The further developing execution by diminishing the number of stages in the deciphering system, diminishing the intricacy of the implementation of the Field Programmable Gate Array (FPGA).

show abstract

Section: Introductionmentioning

confidence: 99%