Implementation of high speed low power combinational and sequential circuits using reversible logic

Shah, Hardik; Rao, A.; Deshpande, Mayuresh; Rane, Ameya; Nagvekar, Siddhesh

doi:10.1109/icaee.2014.6838457

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“…Multiplication by this technique of a 2 figure integer by another 2 figures integer is done as follows [4], [6], [8]:…”

Section: B Urdhwa-tiryakbhammentioning

confidence: 99%

An Efficient Approach to an 8-Bit Digital Multiplier Architecture based on Ancient Indian Mathematics

Telharkar¹,

Telharkar²,

Pednekar³

2015

IJERT

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This paper encompasses the implementation of a novel approach to an 8-bit digital multiplier based on Ancient Indian mathematical algorithm (also known as the Vedic sutra) and its comparison with 2 other conventional multipliers. Since multiplication has become a fundamental function in applications such as Fourier transform, Arithmetic Logic Unit (ALU) architecture and in various sequential clocked circuits, an efficient multiplication technique is a major concern for computer architects. The three multipliers were programmed in Verilog, simulated on Xilinx 14.5 ISE and implemented on 2 FPGA devices, Spartan 3E and Spartan 6. A comparison based on empirical values of delays of each multiplier throws a light on their potential in making the digital circuits substantially efficient.

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“…Multiplication by this technique of a 2 figure integer by another 2 figures integer is done as follows [4], [6], [8]:…”

Section: B Urdhwa-tiryakbhammentioning

confidence: 99%