Implications of Proximity Effects for Analog Design

Drennan, P.G.; Kniffin, Margaret L.; Locascio, D. R.

doi:10.1109/cicc.2006.320869

Cited by 97 publications

(30 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For example, the drain current of a deep-submicron MOSFET device can no longer be predicted by the long-channel models [12], due to various effects including carrier velocity saturation, vertical-field induced mobility degradation, drain-induced barrier lowering (DIBL), and narrow channel effects, only to name a few. In addition, the characteristics of each individual device can be further affected by random variability and proximity effects [13]. Hence, it is extremely difficult to design an optimal circuit in the presence of these complex phenomena without relying on computational aids, e.g.…”

Section: Leveraging Intent For Design Optimizationmentioning

confidence: 99%

Leveraging designer's intent: A path toward simpler analog CAD tools

Kim

Jeeradit

Lim

et al. 2009

2009 IEEE Custom Integrated Circuits Conference

View full text Add to dashboard Cite

Leveraging the Boolean intent of digital circuits has enabled a wide set of CAD tools that helped increase the productivity of digital designers. To increase analog designers' productivity requires a similar encapsulation of designer's intent for analog circuits. We argue that linear system models serve this role for almost all analog circuits, while the variables of these models may be in some transformed domains, rather than being the direct voltage/current waveforms of the circuits. We show how using these models enable new ways to design, optimize, and validate mixed-signal circuits. Even systems that reach steady states only in a stochastic sense can be analyzed as linear systems. Then a remaining issue is to ensure that the non-linear circuit reaches the intended "linear" operating point during start-up, which can be addressed by global convergence analysis.

show abstract

Section: Leveraging Intent For Design Optimizationmentioning

confidence: 99%

Leveraging designer's intent: A path toward simpler analog CAD tools

Kim

Jeeradit

Lim

et al. 2009

2009 IEEE Custom Integrated Circuits Conference

View full text Add to dashboard Cite

show abstract

“…For analog circuits, the variations in process, supply voltage and temperature (PVT) will have considerable impact on offset, linearity, common-mode rejection ratio (CMRR), power supply rejection ratio (PSRR), etc. For 90 nm and below, layout effects such as well proximity effect (WPE) and shallow-trench isolation (STI) stress will result in bias-point shifts of 20-30% in analog circuits [7]. It is shown in [8] that though STI-stress causes large deviation in drain current and threshold voltage, it does not contribute to random mismatch.…”

Section: Process Variationsmentioning

confidence: 99%

Building Blocks for Low-Voltage Analog-to-Digital Interfaces

Harikumar

2014

Linköping Studies in Science and Technology. Thesis

View full text Add to dashboard Cite

In today's system-on-chip (SoC) implementations, power consumption is a key performance specification. The proliferation of mobile communication devices and distributed wireless sensor networks has necessitated the development of power-efficient analog, radio-frequency (RF), and digital integrated circuits. The rapid scaling of CMOS technology nodes presents opportunities and challenges. Benefits accrue in terms of integration density and higher switching speeds for the digital logic. However, the concomitant reduction in supply voltage and reduced gain of transistors pose obstacles to the design of highperformance analog and mixed-signal circuits such as analog front-ends (AFEs) and data converters.To achieve high DC gain, multistage amplifiers are becoming necessary in AFEs and analog-to-digital converters (ADCs) implemented in the latest CMOS process nodes. This thesis includes the design of multistage amplifiers in 40 nm and 65 nm CMOS processes. An AFE for capacitive body-coupled communication is presented with transistor schematic level results in 40 nm CMOS. The AFE consists of a cascade of amplifiers to boost the received signal followed by a Schmitt trigger which provides digital signal levels at the output. Low noise and reduced power consumption are the important performance criteria for the AFE. A two-stage, single-ended amplifier incorporating indirect compensation using split-length transistors has been designed. The compensation technique does not require the nulling resistor used in traditional Miller compensation. The AFE consisting of a cascade of three amplifiers achieves 57.6 dB DC gain with an input-referred noise power spectral density (PSD) of 4.4 nV/ √ Hz while consuming 6.8 mW.Numerous compensation schemes have been proposed in the literature for multistage amplifiers. Most of these works investigate frequency compensation of amplifiers which drive large capacitive loads and require low unity-gain frequency. In this thesis, the frequency compensation schemes for high-speed, lowvoltage multistage CMOS amplifiers driving small capacitive loads have been investigated. Existing compensation schemes such as the nested Miller compensation with nulling resistor (NMCNR) and reversed nested indirect compensation (RNIC) have been applied to four-stage and three-stage amplifiers designed in 40 nm and 65 nm CMOS, respectively. The performance metrics used for comparing the different frequency compensation schemes are the unity gain frequency, phase margin (PM), and total amount of compensation capacitance used. From transistor schematic simulation results, it is concluded that RNIC is more efficient than NMCNR.Successive approximation register (SAR) analog-to-digital converters (ADCs) are becoming increasingly popular in a wide range of applications due to their high power efficiency, design simplicity and scaling-friendly architecture. Singlechannel SAR ADCs have reached high resolutions with sampling rates exceeding 50 MS/s. Time-interleaved SAR ADCs have pushed beyond 1 GS/s with medium r...

show abstract

“…Common compact transistor models, such as BSIM3, can be applied since this stress is constant. For reflecting local proximity effects of stress, the model generation BSIM4 has been introduced [4]. In contrast, variable mechanical stress is evident in many sensing devices, such as for pressure and acceleration, though compact modeling is far less detailed in the design of sensor systems as compared to digital and analog circuit design [5].…”

Section: Introductionmentioning

confidence: 99%