Importance of $\Delta V_{{\text {DIBLSS}}}/({I}_{{\text {on}}} /{I}_{{\text {off}}})$ in Evaluating the Performance of n-Channel Bulk FinFET Devices

Eng, Yi-Chuen; Hu, Luke; Chang, Tzu-Feng; Hsu, Steven; Chiou, Chun Mao; Wang, Ted; Yang, Chih-Wei; Cheng, Osbert; Wang, Chih-Yi; Tseng, Chun-Kai; Huang, Ren Tsung; Lin, Po-Hsieh; Lu, Kuan-Yu; Chang, I.H.; Lee, Chi-Ju; Wu, Yen-Liang; Chang, Man Kit

doi:10.1109/jeds.2018.2789922

Cited by 28 publications

(21 citation statements)

References 14 publications

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“…Hence a V DIBLSS /(I on /I off ) of about 10 −4 mV is obtained. These results are described in [2]. If a highly scaled transistor cannot meet the requirements mentioned above, we may say that the poor short-channel performance is expected and acts as a bottleneck for further scaling [5], [6].…”

Section: Introductionmentioning

confidence: 95%

“…The expression, V DIBLSS /(I on /I off ), was introduced to evaluate the performance of scaled metal-oxide-semiconductor field-effect transistors (MOSFETs) [1], [2]. Four key parameters extracted from MOSFET subthreshold characteristics are combined into a single parameter reflecting the performance.…”

Section: Introductionmentioning

confidence: 99%

“…As the gate length is reduced, the value of the V DIBLSS needs to be as small as 100 mV. The reason for this requirement is to maintain gate control over the channel potential barrier height [2]- [4]. As a result, the value of the I on /I off should be 10 6 .…”

Section: Introductionmentioning

confidence: 99%

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Monitoring of FinFET Characteristics Using $\Delta V_{\text{DIBLSS}}/(I_{\text{on}}/I_{\text{off}})$ and $\Delta V_{\text{DIBL}}/(I_{\text{on}}/I_{\text{off}})$

Eng

Chang

et al. 2019

IEEE J. Electron Devices Soc.

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In this paper, we present a descriptive analysis of a performance index, V DIBLSS /(I on /I off), used for performance monitoring. Scaled n-and p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) (planar and FinFET devices) are included for comparison of performance trends. Also, the simplified V DIBL /(I on /I off) for monitoring the electrical characteristics of MOSFET devices is proposed due to the "quick measurements" required in the last step of the semiconductor manufacturing process. V DIBL /(I on /I off) only accounts for drain-induced barrier lowering in its numerator and on/off current ratio in its denominator. The calculation process for V DIBL /(I on /I off) is much quicker than for V DIBLSS /(I on /I off), where we need to make an extra measurement of the value of the subthreshold swing. Performance metrics, such as I on /I off and intrinsic gain, g m × r o , are reported using V DIBLSS /(I on /I off) and V DIBL /(I on /I off). V DIBLSS of about 100 mV in scaled MOSFETs is required to ensure that the gate control is strong. Since I on /I off is a sensitive function of threshold voltage, the estimates of the V DIBLSS /(I on /I off) and V DIBL /(I on /I off) are therefore dependent on the design of threshold voltage. In planar MOSFETs, small values of V DIBLSS /(I on /I off) and V DIBL /(I on /I off) are hard to achieve. However, in FinFETs, it is easy to achieve the performance requirements due to its tri-gate structure. INDEX TERMS V DIBL /(I on /I off), V DIBLSS /(I on /I off), FinFETs, intrinsic gain, performance metrics, scaled MOSFETs.

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Section: Introductionmentioning

confidence: 95%

Section: Introductionmentioning

confidence: 99%

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Monitoring of FinFET Characteristics Using $\Delta V_{\text{DIBLSS}}/(I_{\text{on}}/I_{\text{off}})$ and $\Delta V_{\text{DIBL}}/(I_{\text{on}}/I_{\text{off}})$

Eng

Chang

et al. 2019

IEEE J. Electron Devices Soc.

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“…The perfect V-curve for n-FinFET and p-FinFET have established for saturation (at 0.75 V) and linear (at 50 mV) operation as congregated in Figures 6 and 7. The similar performances for both devices are realized due to work function engineering using a mid-gap band of 4.6 eV and are outlined in Table 4 (Eng et al, 2018;Knoblinger et al, 2008). It has been reported that enhancement in value of work function and high-k gate dielectric material improves the current ratio and lessens device's SS (Kaur et al, 2020a, b).…”

Section: Performance Optimization Of N-finfet and P-finfet Devices Usmentioning

confidence: 67%

“…The percentage reductions of 10 and 76% for SS and DIBL, respectively, have been achieved in comparison to SiO 2 . The smaller DIBL results in low leakage current and lower SS leading to better on/off switching performance (Zhao et al, 2011;Kaur et al, 2018Kaur et al, , 2020aKaur et al, , 2020bAujla and Kaur, 2019;Eng et al, 2018). The enhanced I ON leads to better g m , as it decides the transistor's gain and operating speed.…”

Section: Impact Of Conventional and Novel Dielectric Oxides On N-finfmentioning

confidence: 99%

Impact of lanthanum doped zirconium oxide (LaZrO₂) gate dielectric material on FinFET inverter

Kaur

Gill

Rattan

2020

International Journal on Smart Sensing and Intelligent Systems

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Fin-typed field effect transistor (FinFET) has considered a suitable device for low power and high-performance applications. The incorporation of gate dielectric lanthanum doped zirconium oxide (LaZrO 2) in the 14 nm silicon on insulator (SOI) FinFET not only enhanced effective carrier mobility but also diminished the short channel effects (SCEs). The FinFET embodiment with LaZrO 2 has dwindled subthreshold swing (SS), reduced drain-induced barrier lowering (DIBL), and raised on-current to off-current ratio as a contrast to SiO 2-based FinFET. A remarkable enhancement of 1.18×, 11×, and 1.3× for transconductance (g m), early voltage (V EA), and an intrinsic gain (A V), respectively, have been investigated. Further, LaZrO 2-based n-FinFET and p-FinFET devices have devised with equal dimensions. The improved noise margin of 0.375 V using a single-fin FinFET-based inverter circuit has proven the acceptance of this device in a circuit application.

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The beneficial impact of a p–p ⁺ junction on DC and analog/radio frequency performance of a vertical super‐thin body FET

Barman

Baishya

2021

Int J RF Microw Comput Aided Eng

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This article investigates the impact of the p-p + junction (at the body-substrate interface) on different direct current (DC) and analog/radio frequency (RF) performance parameters of a newly invented structure called vertical superthin body field effect transistor (VSTB FET) through a well-calibrated TCAD tool. At a fixed body doping, the influence of p-p + junction was inspected for different substrate doping (N s ); which reveals that N s has a robust control on the device electrostatics. Interestingly, higher N s is seen to significantly suppress different short channel effects (SCEs), which in turn helps to improve various DC parameters excellently. An increase in N s from 10 15 to 10 18 cm À3 improves off-state leakage current and on-to-off current ratio by three orders of magnitude. Also, such a change in N s decreases subthreshold swing and drain-induced-barrier-lowering by 8.78 mV/dec and 11.15 mV/V, respectively. The underlying physics behind such improvement at higher N s is explored through the off-state channel electron density profiles corresponding to different N s values. Further, different analog/RF parameters such as transconductance, input capacitance, gate-drain capacitance, output conductance, gain-bandwidth-product, and transconductance frequency product (TFP) show slight improvement for increasing N s . In contrast, TGF, GFP, and GTFP offer large enhancement at higher N s . This study is expected to demonstrate the significance of N s on device performance.

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Importance of $\Delta V_{{\text {DIBLSS}}}/({I}_{{\text {on}}} /{I}_{{\text {off}}})$ in Evaluating the Performance of n-Channel Bulk FinFET Devices

Cited by 28 publications

References 14 publications

Monitoring of FinFET Characteristics Using $\Delta V_{\text{DIBLSS}}/(I_{\text{on}}/I_{\text{off}})$ and $\Delta V_{\text{DIBL}}/(I_{\text{on}}/I_{\text{off}})$

Monitoring of FinFET Characteristics Using $\Delta V_{\text{DIBLSS}}/(I_{\text{on}}/I_{\text{off}})$ and $\Delta V_{\text{DIBL}}/(I_{\text{on}}/I_{\text{off}})$

Impact of lanthanum doped zirconium oxide (LaZrO₂) gate dielectric material on FinFET inverter

The beneficial impact of a p–p ⁺ junction on DC and analog/radio frequency performance of a vertical super‐thin body FET

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Importance of $\Delta V_{{\text {DIBLSS}}}/({I}_{{\text {on}}} /{I}_{{\text {off}}})$ in Evaluating the Performance of n-Channel Bulk FinFET Devices

Cited by 28 publications

References 14 publications

Monitoring of FinFET Characteristics Using $\Delta V_{\text{DIBLSS}}/(I_{\text{on}}/I_{\text{off}})$ and $\Delta V_{\text{DIBL}}/(I_{\text{on}}/I_{\text{off}})$

Monitoring of FinFET Characteristics Using $\Delta V_{\text{DIBLSS}}/(I_{\text{on}}/I_{\text{off}})$ and $\Delta V_{\text{DIBL}}/(I_{\text{on}}/I_{\text{off}})$

Impact of lanthanum doped zirconium oxide (LaZrO2) gate dielectric material on FinFET inverter

The beneficial impact of a p–p + junction on DC and analog/radio frequency performance of a vertical super‐thin body FET

Contact Info

Product

Resources

About

Impact of lanthanum doped zirconium oxide (LaZrO₂) gate dielectric material on FinFET inverter

The beneficial impact of a p–p ⁺ junction on DC and analog/radio frequency performance of a vertical super‐thin body FET