Improved analog and AC performance with increased noise immunity using nanotube junctionless field effect transistor (NJLFET)

Rewari, Sonam; Nath, Vandana; Haldar, Subhasis; Deswal, S. S.; Gupta, Rashmi

doi:10.1007/s00339-016-0583-9

Cited by 37 publications

(10 citation statements)

References 18 publications

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“…This higher change in the drain current owes to the core shell nanotube FET structure which has two gates. This potential elevates the lateral electric field [26,27] and also the gate transport efficiency, thereby enhancing the drain current. Figure 6 pictures Ratio of I ON /I OFF for the contemplated device designs under channel lengths.…”

Section: Siliconmentioning

confidence: 99%

Core-Shell Nanowire Junctionless Accumalation Mode Field-Effect Transistor (CSN-JAM-FET) for High Frequency Applications - Analytical Study

Rewari

2020

Silicon

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Here, an analytical model has been proposed for Core-Shell-Nanowire-Junctionless-Accumulation-Mode-Field-Effect Transistor (CSN-JAM-FET) for High Frequency Applications. CSN-JAM-FET has been contrasted with Nanowire-Junctionless-Accumulation-Mode-Field-Effect Transistor (NJAM-FET) under the similar device conditions by keeping the threshold voltage same for both. It is so found that CSN-JAM-FET shows much higher drain current (I ds ), transconductance (g m ), output conductance (g d ), I on /I off ratio, Subthreshold Slope (SS) and cut off frequency (f T ) because of the inherent property of core shell architecture to elevate the gate domination over the channel. The analytical results have also been modelled for CSN-JAM-FET by finding a result of the Two-Dimensional Poisson equation in accordance with the boundary conditions. The analytical results are much in coherence with the results obtained from the simulator.

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Section: Siliconmentioning

confidence: 99%

Core-Shell Nanowire Junctionless Accumalation Mode Field-Effect Transistor (CSN-JAM-FET) for High Frequency Applications - Analytical Study

Rewari

2020

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“…Our simulation results show that Ga0.8In0.2As/Ga0.85In0.15Sb VHJL-TFET proposed here with a 30nm channel length has ION=8mA/µm. The ION Ga0.8In0.2As/Ga0.85In0.15Sb VHJL-TFET is higher than that of the recently proposed devices [28,36]. Consequently, there is no low ION restriction in proposed Ga0.8In0.2As/Ga0.85In0.15Sb VHJL-TFET device.…”

Section: 4sensitivity Analysismentioning

confidence: 80%

“…ION of Ga0.8In0.2As/Ga0.85In0.15Sb VHJL-TFET proposed in this paper is compared with the devices, in which the current mechanism is thermionic emission. Nanotube junctionless FET (NJLFET) proposed in [36] with 30nm gate length has ION=24.9 µA. Junctionless field effect diode (JL-FED) proposed in [28] with a 30nm channel length has ION=0.1mA/µm.…”

Section: 4sensitivity Analysismentioning

confidence: 99%

Investigation of the impact of mole-fraction on the digital benchmarking parameters as well as sensitivity in GaXIn1−XAs/GaYIn1−YSb vertical heterojunctionless tunneling field effect transistor

Rajabi

Vadizadeh

2021

Int. J. Mod. Phys. B

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Ga[Formula: see text]In[Formula: see text]As/Ga[Formula: see text]In[Formula: see text]Sb vertical heterojunctionless tunneling field effect transistor (VHJL-TFET) has been suggested to optimize the digital benchmarking parameters. In the proposed VHJL-TFET with type II heterostructure (i.e., [Formula: see text] and [Formula: see text]), slight changes in gate voltage cause switching from OFF-state to ON-state. As a result, the electrical properties of Ga[Formula: see text]In[Formula: see text]As/Ga[Formula: see text]In[Formula: see text]Sb VHJL-TFET are excellent in the sub-threshold region. The heterostructure with III–V semiconductors in the source-channel region increases the ON-state current ([Formula: see text]) of the VHJL-TFET. Comparing the results of Ga[Formula: see text]In[Formula: see text]As/Ga[Formula: see text]In[Formula: see text]Sb VHJL-TFET with the simulated devices with type I heterostructure (i.e., [Formula: see text] and [Formula: see text]) and type III heterostructure (i.e., [Formula: see text] and [Formula: see text]) shows the improvement by 26% and 15% in the average subthreshold slope (SS). Sensitivity analysis for VHJL-TFET with the type II heterostructure shows that the sensitivity of OFF-state current ([Formula: see text] to the body thickness ([Formula: see text] and doping concentration ([Formula: see text] is more than the sensitivity of the other main electrical parameters. The Ga[Formula: see text]In[Formula: see text]As/Ga[Formula: see text]In[Formula: see text]Sb VHJL-TFET with a channel length of 20 nm, [Formula: see text] nm, and [Formula: see text] cm[Formula: see text] showed the [Formula: see text] mV/dec, [Formula: see text]/[Formula: see text], and [Formula: see text] mA/um. As a result, Ga[Formula: see text]In[Formula: see text]As/Ga[Formula: see text]In[Formula: see text]Sb VHJL-TFET can be a reasonable choice for digital applications.

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“…10 depicts the early voltage shift as a function of gate bias. A greater VEA indicates that the device will have higher gain and can be used in amplifiers [46]. Fig.…”

Section: Fig 9 Tgf As a Function Of Vgsmentioning

confidence: 99%

“…As can be observed from the figure that the JAM-FE-FET exhibits lower channel resistance owing to its increased carrier density and velocity in the channel region. The next figure of merit is the intrinsic dc gain which can be defined as the transconductance (gm) to output conductance (gd) ratio, i.e., gm/gd [46]. Since gd is extracted from static Id-Vds curve, so it is the low frequency or quasi-static result.…”

Section: Fig 9 Tgf As a Function Of Vgsmentioning

confidence: 99%

Junctionless Accumulation Mode Ferroelectric FET (JAM-FE-FET) for High Frequency Digital and Analog Applications

Yadav

Rewari

Pandey

2022

Silicon

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In this paper, a Junctionless Accumulation Mode Ferroelectric Field Effect Transistor (JAM-FE-FET) has been proposed and assessed in terms of RF/analog specifications for varied channel lengths through simulations using TCAD Silvaco ATLAS simulator, using the Shockley-Read-Hall (SRH) recombination, ferro, Lombardi CVT, fermi and LK models. Major analog metrics like transconductance (gm), intrinsic gain (AV), output conductance (gd), and early voltage (VEA) are obtained for the JAM-FE-FET arrangement. The proposed structure shows an improvement in parameters like gm, Ion/Ioff, Av, TGF by 6.82%, 27.95%, 5.2%, 38.83% respectively. Further, frequency analysis of the proposed device is performed and several critical RF parameters like fT, TFP, GFP, and GTFP have been observed to be enhanced by 6.89%, 11.38%, 13.65%, 12.01% respectively. Thus, the Junctionless accumulation mode ferroelectric FET (JAM-FE-FET) arrangement has been found to have superior analog and RF performance when compared to Junctionless ferroelectric FET(JL-FE-FET). As a result, the JAM-FE-FET device presented here can be contemplated a good contender for applications in high-frequency systems.

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Improved analog and AC performance with increased noise immunity using nanotube junctionless field effect transistor (NJLFET)

Cited by 37 publications

References 18 publications

Core-Shell Nanowire Junctionless Accumalation Mode Field-Effect Transistor (CSN-JAM-FET) for High Frequency Applications - Analytical Study

Core-Shell Nanowire Junctionless Accumalation Mode Field-Effect Transistor (CSN-JAM-FET) for High Frequency Applications - Analytical Study

Investigation of the impact of mole-fraction on the digital benchmarking parameters as well as sensitivity in GaXIn1−XAs/GaYIn1−YSb vertical heterojunctionless tunneling field effect transistor

Junctionless Accumulation Mode Ferroelectric FET (JAM-FE-FET) for High Frequency Digital and Analog Applications

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