Improvement of Deep-Trench LDMOS With Variation Vertical Doping for Charge-Balance Super-Junction

Cheng, Junji; Chen, Weizhen; Li, Ping

doi:10.1109/ted.2018.2802485

Cited by 18 publications

(5 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…DT SJ LDMOS, some other reported structures [12−18] and DC DT SJ LDMOS proposed in this paper. From the figure it can be seen that the electrical performance of the device breaks through the "silicon limit" [11] .…”

Section: Results Of the Simulationmentioning

confidence: 99%

A deep trench super-junction LDMOS with double charge compensation layer

Wu¹,

Su²,

Chen³

et al. 2022

J. Semicond.

View full text Add to dashboard Cite

A deep trench super-junction LDMOS with double charge compensation layer (DC DT SJ LDMOS) is proposed in this paper. Due to the capacitance effect of the deep trench which is known as silicon–insulator–silicon (SIS) capacitance, the charge balance in the super-junction region of the conventional deep trench SJ LDMOS (Con. DT SJ LDMOS) device will be broken, resulting in breakdown voltage (BV) of the device drops. DC DT SJ LDMOS solves the SIS capacitance effect by adding a vertical variable doped charge compensation layer and a triangular charge compensation layer inside the Con. DT SJ LDMOS device. Therefore, the drift region reaches an ideal charge balance state again. The electric field is optimized by double charge compensation and gate field plate so that the breakdown voltage of the proposed device is improved sharply, meanwhile the enlarged on-current region reduces its specific on-resistance. The simulation results show that compared with the Con. DT SJ LDMOS, the BV of the DC DT SJ LDMOS has been increased from 549.5 to 705.5 V, and the R on,sp decreased to 23.7 mΩ·cm2.

show abstract

Section: Results Of the Simulationmentioning

confidence: 99%

A deep trench super-junction LDMOS with double charge compensation layer

Wu¹,

Su²,

Chen³

et al. 2022

J. Semicond.

View full text Add to dashboard Cite

show abstract

“…Based on the common structure of T-LDMOS, many improved structures are proposed [4]- [12], such as the ones with vertical field plates in the trench [7]- [9], and the ones with variable-k trench-dielectric [10]- [12]. Recently, many studies start applying a well-known technique of super junction (SJ) to the LDMOS [13]- [16], as well as to the T-LDMOS [17]- [20], such as the T-LDMOS with a quasi vertical (QV) SJ structure [17], [19], [20] and that with a lateral SJ structure at the trench bottom [18]. However, because the trench acts as a capacitor in the off-state and disturbs the surface electric-field (e-field) distribution [19], a QVSJ structure in T-LDMOS is hard to satisfy the important charge-balanced condition and, therefore, cannot be fully used to improve the device performance.…”

Section: Introductionmentioning

confidence: 99%

“…Recently, many studies start applying a well-known technique of super junction (SJ) to the LDMOS [13]- [16], as well as to the T-LDMOS [17]- [20], such as the T-LDMOS with a quasi vertical (QV) SJ structure [17], [19], [20] and that with a lateral SJ structure at the trench bottom [18]. However, because the trench acts as a capacitor in the off-state and disturbs the surface electric-field (e-field) distribution [19], a QVSJ structure in T-LDMOS is hard to satisfy the important charge-balanced condition and, therefore, cannot be fully used to improve the device performance. Although some studies have paid attention to deal with that, they mostly rely on some costly process to realize the complex structures, such as the drift region with the variation vertical doping [19] and the trapezoidal trench [20].…”

Section: Introductionmentioning

confidence: 99%

“…However, because the trench acts as a capacitor in the off-state and disturbs the surface electric-field (e-field) distribution [19], a QVSJ structure in T-LDMOS is hard to satisfy the important charge-balanced condition and, therefore, cannot be fully used to improve the device performance. Although some studies have paid attention to deal with that, they mostly rely on some costly process to realize the complex structures, such as the drift region with the variation vertical doping [19] and the trapezoidal trench [20].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Trench LDMOS Improved by Quasi Vertical Super Junction and Resistive Field Plate

Cheng

Chen

et al. 2019

IEEE J. Electron Devices Soc.

Self Cite

View full text Add to dashboard Cite

An improved trench lateral double-diffused MOSFET (T-LDMOS) is proposed. It has a quasi vertical super junction (QVSJ) drift region and adopts a resistive field plate (RFP) to help QVSJ satisfy charge-balance. The realization of RFP barely complicates the device fabrication, but it motivates QVSJ to significantly improve the relationship between breakdown voltage (BV) and specific on-state resistance (R ON,SP). The simulation results show that compared with the conventional QVSJ T-LDMOS, the proposed one gains the R ON,SP reduced by about 79% under the same BV requirement of about 500 V. It therefore presents an excellent figure of merit (FOM) (FOM = BV 2 /R ON,SP , Baliga's FOM) up to 29.8 MW/cm 2 , which is superior to the prior art and exhibits a bright prospect of saving energy. INDEX TERMS Trench LDMOS (T-LDMOS), quasi vertical super junction (QVSJ), resistive field plate (RFP).

show abstract

“…The BV of the power device is limited by the low lateral BV for the poor surface electric field distribution, and some work has been carried out, such as the variable lateral doping (VLD), [4][5][6][7] super junction, [8,9] and charge islands. [10] Enhancing the electric field (ENDIF) of the dielectric buried layer is a feasible method to increase the vertical BV and several new structures have been developed [11][12][13][14][15] in which introducing self-adaptive interface charges are effective and attractive.…”

Section: Introductionmentioning

confidence: 99%

Stacked lateral double-diffused metal-oxide-semiconductor field effect transistor with enhanced depletion effect by surface substrate

Li¹,

Zhang²,

Li³

et al. 2019

Chinese Phys. B

View full text Add to dashboard Cite

A stacked lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS) with enhanced depletion effect by surface substrate is proposed (ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches (SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance (R on,sp ). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage (BV). Compared to a conventional LDMOS (C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The R on,sp decreases from 39.62 mΩ•cm 2 to 23.24 mΩ•cm 2 and the Baliga's figure of merit (FOM) of is 9.07 MW/cm 2 .

show abstract

Improvement of Deep-Trench LDMOS With Variation Vertical Doping for Charge-Balance Super-Junction

Cited by 18 publications

References 17 publications

A deep trench super-junction LDMOS with double charge compensation layer

A deep trench super-junction LDMOS with double charge compensation layer

A Trench LDMOS Improved by Quasi Vertical Super Junction and Resistive Field Plate

Stacked lateral double-diffused metal-oxide-semiconductor field effect transistor with enhanced depletion effect by surface substrate

Contact Info

Product

Resources

About