Improvement of solder joint reliability between multilayer ceramic package and printed wiring board by new ceramic material

Yamaguchi, Kouichi; Higashi, Mitsutoshi; Yonekura, H.; Hamada, N.; Kunimatsu, Y.

doi:10.1109/ectc.1997.606340

Cited by 5 publications

(4 citation statements)

References 1 publication

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“…The multilayered substrate with inner via holes in any layers like a multilayered ceramic substrate is suitable for the CSP interposer. Matsushita has already developed an ALIVH substrate which is a multilayered organic substrate with inner via holes in any layers [8]. The schematic diagram of the ALIVH substrate is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Packaging properties of ALIVH-CSP using SBB flip-chip bonding technology

Itagaki

Amami

Tomura

et al. 1999

IEEE Trans. Adv. Packag.

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A new chip scale package (CSP) using an organic laminated substrate called CSP was developed, which was fabricated using ALIVH substrate as a interposer and stud-bumpbonding (SBB) flip-chip technology. The ALIVH substrate is a multilayered organic substrate with inner via holes in any layer. The newly developed CSP-L using ALIVH substrate had realized a miniaturization of its package size same as a CSP using a ceramic substrate (CSP-C). In order to perform the SBB flipchip bonding onto the ALIVH substrate, an excellent coplanarity of the substrate surface was required. The required coplanarity was obtained using a fixture during the SBB flip-chip bonding process. The first-level packaging reliability and the second-level packaging reliability onto ALIVH mother board were evaluated. The resulting reliabilities were good enough to apply to the practical use.

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Section: Introductionmentioning

confidence: 99%

Packaging properties of ALIVH-CSP using SBB flip-chip bonding technology

Itagaki

Amami

Tomura

et al. 1999

IEEE Trans. Adv. Packag.

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“…On the other hand, the ceramic substrate with a high coefficient of thermal expansion (CTE) is desirable for a high second level reliability needs so that the thermal mismatch between ceramic substrate and the mother board (FR4 is usually used) is reduced. A high CTE ceramic substrate with a CTE value of 10~12ppm/C is thereby introduced [1]. This kind of structure has been studied for both tin-lead and leadfree applications [2~6].…”

Section: Introductionmentioning

confidence: 99%

“…For Sn-Pb solder, a well-known prediction model using Norris-Landzberg's equation has been proposed by John et al as shown in Equation 1 [7]. (1) where, N is the life in cycles,…”

Section: Introductionmentioning

confidence: 99%

Reliability study of high-end Pb-free CBGA solder joint under various thermal cycling test conditions

Xie

Gektin

Geiger

2009

2009 59th Electronic Components and Technology Conference

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This paper described a ceramic ball grid array (CBGA) and its second level reliability. The CBGA uses a substrate with high coefficient of thermal expansion (CTE) and leadfree soldering. The reworkability of the BGA package and board was also studied. The results have shown that this package is reworkable without a significant reliability reduction in the board level reliability. The reliability of solder joints in different chains is monitored and reported separately during the thermal cycling test to understand the impact of the distance to the neutral point.A finite element model of the test setup was created and modeling results were compared with the thermal cycling reliability test data. Acceleration factor has calculated for irregular temperature profiles as compared to the standard ATC profile. The impact of the highest temperature during the temperature cycle as well as the temperature range was shown to follow traditional Norris-Landzberg's equation. A recommendation is made to use the acceleration factor for translating the test data between different temperature cycling scenarios.978-1-4244-4476-2/09/$25.00 ©2009 IEEE

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“…To reduce the inelastic strain, we have developed a HITCE ceramic material [4][5]. This material enables a tine and flexible design for a package of high performance and high reliability.…”

Section: Introductionmentioning

confidence: 99%

The application of HITCE ceramic material for LGA-type chip scale package

Maeda

Higashi

Kokubu

et al.

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)

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Needs for the Chip Scale Package (CSP) is acceleratingly increased in the package market, where low cost, light weight, smaller, and thinner package is required. The increasing signal performance and number of functions of a signal processing system also require higher pin count and higher wiring density. To satisfy these needs, we have developed a high thermal coefficient of expansion (TCE) ceramic material, HITCE. This material enables a fine and flexible design of a package for high performance, and high reliability.We have investigated the most appropriate assembly design of the HITCE CSP, by finite element method (FEM) analyses, considering a creep characteristics of solder. According to the analyses, we confirmed that the inelastic strain of solder bump is considerably reduced by a HITCE material of low Young's modulus and high TCE. Especially by the HITCE, we found that the inelastic strain of solder for Land Grid Array (LGA) becomes smaller than the inelastic strain of a Ball Grid Array (BGA) solder bump, which is essential for higher reliability of the second level mounting. HITCE ceramic is expected to be the most appropriate material to keep the heigh of solder joint low for a thinner CSP.To confirm the analytical results, we prepared a BGA-type CSP and a LGA-type CSP, and carried out temperature cycling tests (TCT). The result has shown that the first level reliability of HITCE CSP satisfies JEDEC level 1 requirement. Moreover, the second level reliability results revealed that LGA-type CSP has higher solder joint reliability than that of BGA-type CSP.The LGA-type HITCE CSP can be mounted on a printed wiring board (PWB) simply with a printed solder paste, with no ball attaching process. Low cost and low height assembly, and high wiring density for a LGA-type CSP is available by adopting the HITCE materials. IntroductionNeeds for the CSP is rapidly increasing in the IC package market, where low cost, light weight, smaller, and thinner package are required. The increasing signal performance and number of function of a signal processing system also require higher pin count and higher wiring density.For the CSP, fine pitch BGA-type mountings are becoming the mainstream in these days. However, increase in number of I10 counts and the decrease in package size are two major trends for the coming higher density packaging, and down sizing of the pad-pitch is almost unavoidable.The BGA-type CSP rely on solid solder balls for the interconnection between the package and a PWB. This ball attaching process inevitably causes a substantially higher cost than the relatively simple lead-frame package. One of the main disadvantages of the solder balls is their poor thermal

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Improvement of solder joint reliability between multilayer ceramic package and printed wiring board by new ceramic material

Cited by 5 publications

References 1 publication

Packaging properties of ALIVH-CSP using SBB flip-chip bonding technology

Packaging properties of ALIVH-CSP using SBB flip-chip bonding technology

Reliability study of high-end Pb-free CBGA solder joint under various thermal cycling test conditions

The application of HITCE ceramic material for LGA-type chip scale package

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