Improving utilization of reconfigurable resources using two-dimensional compaction

Abstract

Partial reconfiguration allows parts of the reconfigurable chip area to be configured without affecting the rest of the chip. This allows placement of tasks at run time on the reconfigurable chip. Area management is a very important issue which highly affect the utilization of the chip and hence the performance.This paper focuses on a major aspect of moving running tasks to free space for new incoming tasks (compaction). We study the effect of compacting running tasks to free more contiguous space on the system performance. First, we introduce a straightforward compaction strategy called Blind compaction. We use its performance as a reference to measure the performance of other compaction algorithms. Then we propose a two-dimensional compaction algorithm called one-corner compaction. This algorithm runs with respect to one chip corner. We further extend this algorithm to the four corners of the chip and introduce the four-corners compaction algorithm. Finally, we compare the performance of these algorithms with some existing compaction strategies: ). The simulation results show improvement in average task allocation time when using the four-corners compaction algorithm by 15% and in chip utilization by 16% over the Blind compaction. These results outperform the existing strategies.

New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA

“…Consequently, there are three categories of hardware tasks. [4] -Device cells: 100 × 100 13% ----100 tasks -Task size: 17 × 17 Genetic algorithm [10] -Device cells: 64 × 64 45% 60%-80% ---Sets of 3,000 tasks -Task size: 32 × 32 Heuristics KAMER-BF [4] -Device cells: 100 × 100 13%-18% --O(n log(n))n: number of tasks on the device -2048-16384 tasks -Task size: 17 × 17 Blind compaction [1] -Device cells: 64 × 64 -60% -O(n 2 )n: number of tasks on the device -10.000 tasks -Task size: 32 × 32 IM [8] -Device cells: 100 × 100 10% ----13 task sets each of 1000 tasks -Task size: 2 × 2 − 20 × 20 Configuration Reuse + Configuration Prefetch [11] - The features of hardware tasks and their instances are presented in Table 2. These hardware tasks are characterized by considering the resource area in Virtex 5 technology [29].…”

“…In opposition to [11,32], our multiobjective placement computes the configuration overhead in the worst case before scheduling (11%) and targets an application of 14 tasks which is not the case of [11,32] that optimizes the configuration overhead only for two or three tasks during the scheduling (18%, 8%). Comparing to [10] (sets of 3,000 homogeneous tasks) and [1] (10.000 homogeneous tasks) applied in homogeneous devices; we have reduced efficiently the resource utilization (36%) for an application of 14 heterogeneous tasks and by taking into account the heterogeneity of recent reconfigurable devices. The heterogeneous resources in FPGA could fit the RZs on large RPBs giving a significant resource waste.…”

“…The more consistent these parameters are, the higher the cost of RB type. The RB-model of each hardware task is described by (1).…”

“…The development of dynamic partial reconfiguration in the FPGAs allows reconfiguring only the necessary part of the FPGA when required without interfering with any other parts running on the same FPGA. While this technique can increase device utilization and performance of scheduling and application, it also leads to high configuration overhead, fragmentation, and complex allocation situations of hardware tasks [1]. Frequently, the existing methods of placement face these issues.…”

Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence

“…Finally, a number of authors propose to compact the allocated tasks on the FPGA from time to time in a similar way that the hard drive of a computer is defragmented [32][33][34][35][36]. However, defragmentation techniques incur high reconfiguration overhead provoked by extra task relocations.…”