In-Line Metrology for Characterization and Control of Extreme Wafer Thinning of Bonded Wafers

Liebens, M.; Jourdain, Anne; Vos, Joeri De; Vandeweyer, T.; Miller, Andy; Beyne, Eric; Li, S.; Bast, Gerhard; Stoerring, M.; Hiebert, S.; Cross, Andrew

doi:10.1109/tsm.2018.2885577

Cited by 7 publications

(3 citation statements)

References 7 publications

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“…3-D system-on-chip (SoC) enhances interconnection density through Wafer-to-Wafer (W2W) bonding, extreme thinning combined with parallel front-end of line (FEOL) [9], as illustrated in Fig. 1.…”

Section: Preliminariesmentioning

confidence: 99%

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Cost Modeling and Analysis of TSV and Contactless 3D-ICs

Jiang

Papistas

Pavlidis

2020

Proceedings of the 2020 on Great Lakes Symposium on VLSI

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Contactless three-dimensional (3-D) interconnects have been proposed as an alternative to through-silicon via (TSV) due to its manufacturing compatibility with two-dimensional (2-D) processes. Typically, contactless 3-D circuits are thought to require considerable silicon resources compared to TSV. However, recent manufacturing options, such as extreme wafer thinning, provide new opportunities for this approach. This paper, therefore, explores these opportunities for producing 3-D systems of lower cost. The presented cost analysis and models usefully combine fabrication cost with performance requirements for inter-tier communication as a critical component of 3-D systems. Thus, benchmark circuits are simulated for a two-tier system using a commercial 65 𝑛𝑚 technology and communicating at a data rate of 1 𝐺𝑏𝑝𝑠 per link, although the model is directly applicable to any technology or design specifications. Interestingly, inductive links can be a useful alternative to TSV for specific and expected manufacturing capabilities. Furthermore, the effectiveness of different multiplexing schemes and their effect on system cost is also evaluated. CCS CONCEPTS• Hardware → 3D integrated circuits; Radio frequency and wireless interconnect.

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Section: Preliminariesmentioning

confidence: 99%

“…During the extreme thinning process, the silicon thickness of the top wafer is thinned to 5 𝜇m. Due to the very small diameter and pitch of TSV (diameter < 1 𝜇m, pitch < 2 𝜇m), which are approximately 10 times smaller than those of the typical substrate thickness (50 𝜇m) [9], the scaling of TSVs can be significantly extended.…”

Section: Preliminariesmentioning

confidence: 99%

Cost Modeling and Analysis of TSV and Contactless 3D-ICs

Jiang

Papistas

Pavlidis

2020

Proceedings of the 2020 on Great Lakes Symposium on VLSI

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“…The process variation across a wafer may be greater at the edge compared to that at the center, resulting in a higher yield loss at the wafer edge [11]. The thinning process could induce damage at the wafer edge, which would directly impact the physical yield [12]. According to Yavas, several factors can lead to significant edge yield loss.…”

Section: Introductionmentioning

confidence: 99%

Wafer Edge Yield Prediction Using a Combined Long Short-Term Memory and Feed- Forward Neural Network Model for Semiconductor Manufacturing

Kim

2020

IEEE Access

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In semiconductor manufacturing, maintaining a high yield and ensuring accurate yield prediction are considerably important for improving productivity, customer satisfaction, and enhancing profitability. Despite its importance and merits, achieving wafer yield prediction with high quality and accuracy is challenging. In this paper, we propose a method for wafer edge yield prediction using a combined long short-term memory (LSTM) and feed-forward neural network (FFNN) model. Unlike previous research, we focus on the edge yield because of the higher yield loss at the wafer edge. The combined LSTM-FFNN model uses a dataset divided into two types according to data characteristics. Timeseries data are used in the case of LSTM, and non-time-series data are fed into the FFNN. When preparing the time-series data, comprising data related to the equipment and chambers, data of different chambers do not overlap, thereby rendering them as independent entities. The proposed model outperforms other models in terms of all evaluation metrics. The coefficient of determination of the proposed combined LSTM-FFNN model is 34.14%, which is almost 13% higher than that of the other compared models on average.

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Design and Realization of Transient Electronics Enabled by Nanomembranes

You

Zhang

et al. 2022

Nanomembranes

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In-Line Metrology for Characterization and Control of Extreme Wafer Thinning of Bonded Wafers

Cited by 7 publications

References 7 publications

Cost Modeling and Analysis of TSV and Contactless 3D-ICs

Cost Modeling and Analysis of TSV and Contactless 3D-ICs

Wafer Edge Yield Prediction Using a Combined Long Short-Term Memory and Feed- Forward Neural Network Model for Semiconductor Manufacturing

Design and Realization of Transient Electronics Enabled by Nanomembranes

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