We describe challenges of the epitaxial Si-cap/Si0.75Ge0.25//Si-substrate growth process, in view of its application in 3D device integration schemes using Si0.75Ge0.25 as backside etch stop layer with a focus on high throughput epi processing without compromising material quality. While fully strained Si0.75Ge0.25 with a thickness >10 times larger than the theoretical thickness for layer relaxation can be grown, it is challenging to completely avoid misfit dislocations at the wafer edge during Si-growth on top of strained Si0.75Ge0.25, even for thinner Si0.75Ge0.25 layers and when growing the Si-cap layer at a lower temperature. Extremely sensitive characterization methods are mandatory to detect the extremely low density of misfit dislocations at the wafer edge. Light scattering measurements are most reliable. The epitaxial Si-cap/Si0.75Ge0.25//Si-substrate layer stacks are stable against post-epi thermal processing steps, typically applied before wafer-to-wafer bonding and Si-substrate and Si0.75Ge0.25 backside removal.

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