In&lt;inf&gt;0.53&lt;/inf&gt;Ga&lt;inf&gt;0.47&lt;/inf&gt;As MOSFETs with high channel mobility and gate stack quality fabricated on 300 mm Si substrate

Huang, M. L.; Chang, S. W.; Chen, M. K.; Fan, C. H.; Lin, Chia-Hui; Chu, Ronfu; Lee, K. Y.; Khaderbad, Mrunal A.; Chen, Z. C.; Chen, C. H.; Lin, Li-Te; Lin, Hsia Yu; Chang, Hui Cheng; Yang, Chenxue; Leung, Ying K.; Yeo, Yee-Chia; Jang, S. M.; Hwang, H. Y.; Diaz, C.H.

doi:10.1109/vlsit.2015.7223675

Cited by 14 publications

(10 citation statements)

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“…5(c). These results coincide with the experimental observation from a number of groups that single-domain Ge and III-V layers can be deposited on nominal Si (001) substrates [54,55,[64][65][66][67].…”

Section: Wafer-scale Hetero-epitaxial Growth Of Iii-v Thin Ilms On Sisupporting

confidence: 90%

“…Today, 300 mm GaP/Si templates , showing a promising path towards high-eficiency dual-junction GaAsP-on-Si cells. Motivated by the development of III-V channel MOSFETs for high-performance and low-power logic applications, Huang et al [54] and Orzali et al [55] reported epitaxy of smooth In 0.53 Ga 0. 47 As layers on 300 mm Si wafers using metamorphic InP/GaAs bufers by MOCVD.…”

Section: Wafer-scale Hetero-epitaxial Growth Of Iii-v Thin Ilms On Simentioning

confidence: 99%

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Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Lau

2017

Progress in Crystal Growth and Characterization of Materials

125

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Please note: Changes made as a result of publishing processes such as copy-editing, formatting and page numbers may not be reflected in this version. For the definitive version of this publication, please refer to the published source. You are advised to consult the publisher's version if you wish to cite this paper.This version is being made available in accordance with publisher policies. See http://orca.cf.ac.uk/policies.html for usage policies. Copyright and moral rights for publications made available in ORCA are retained by the copyright holders. U N C O R R E C T E D P R O O F ARTICLE INFO ABSTRACTMonolithic integration of III-V on silicon has been a scientifically appealing concept for decades. Notable progress has recently been made in this research area, fueled by significant interests of the electronics industry in high-mobility channel transistors and the booming development of silicon photonics technology. In this review article, we outline the fundamental roadblocks for the epitaxial growth of highly mismatched III-V materials, including arsenides, phosphides, and antimonides, on (001) oriented silicon substrates. Advances in hetero-epitaxy and selective-area hetero-epitaxy from micro to nano length scales are discussed. Opportunities in emerging electronics and integrated photonics are also presented.

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Section: Wafer-scale Hetero-epitaxial Growth Of Iii-v Thin Ilms On Sisupporting

confidence: 90%

Section: Wafer-scale Hetero-epitaxial Growth Of Iii-v Thin Ilms On Simentioning

confidence: 99%

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Lau

2017

Progress in Crystal Growth and Characterization of Materials

125

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“…Virtual SiGe [8], Ge and III-V [9] buffer layers on bulk Si wafers have been demonstrated. Typically, 1-2 µm thick layers need to be grown and post-deposition TDD (threading dislocation density) anneals are required to lower the defect density.…”

Section: Ge and Iii-v Integration On Si Substratesmentioning

confidence: 99%

“…To date, defect densities as low as 10 6 cm´2 have been reported for SiGe [8]. Reported defect levels for III-V on 300 mm Si are, however, significantly higher: 1-2ˆ10 9 cm´2 [9]. The latter substrates also require a more complex stack consisting of combinations of GaAs, InP and InAlAs to fabricate the required top InGaAs channels.…”

Section: Ge and Iii-v Integration On Si Substratesmentioning

confidence: 99%

Mastering the Art of High Mobility Material Integration on Si: A Path towards Power-Efficient CMOS and Functional Scaling

Collaert

2016

JLPEA

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“…Device performance and reliability inevitably suffer from the high-density defects in the hetero-epitaxial III-V materials [14]. To overcome these problems, two main approaches are widely applied for the epitaxy of InP films on Si: one is known as selective area growth (SAG), where InP is grown selectively in the patterning nanometer scale trenches to trap defects at its sidewalls by the defect necking effect [15,16], and the other one is direct growth process by depositing InP directly on blanket Si wafers with metamorphic buffers [17][18][19]. Compared with SAG method, the direct growth process has fewer processing steps without lithography or etching to reduce the risk of contamination.…”

Section: Introductionmentioning

confidence: 99%

Influence of Growth Temperature of the Nucleation Layer on the Growth of InP on Si (001)

Yang

et al. 2019

Coatings

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InP layers grown on Si (001) were achieved by the two-step growth method using gas source molecular beam epitaxy. The effects of growth temperature of nucleation layer on InP/Si epitaxial growth were investigated systematically. Cross-section morphology, surface morphology and crystal quality were characterized by scanning electron microscope images, atomic force microscopy images, high-resolution X-ray diffraction (XRD), rocking curves and reciprocal space maps. The InP/Si interface and surface became smoother and the XRD peak intensity was stronger with the nucleation layer grown at 350 °C. The Results show that the growth temperature of InP nucleation layer can significantly affect the growth process of InP film, and the optimal temperature of InP nucleation layer is required to realize a high-quality wafer-level InP layers on Si (001).

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In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFETs with high channel mobility and gate stack quality fabricated on 300 mm Si substrate

Cited by 14 publications

References 2 publications

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Mastering the Art of High Mobility Material Integration on Si: A Path towards Power-Efficient CMOS and Functional Scaling

Influence of Growth Temperature of the Nucleation Layer on the Growth of InP on Si (001)

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