In-Plane Ferroelectric Tin Monosulfide and Its Application in a Ferroelectric Analog Synaptic Device

Abstract

Two-dimensional ferroelectrics is attractive for synaptic device applications because of its low power consumption and amenability to high-density device integration. Here, we demonstrate that tin monosulfide (SnS) films less than 6 nm thick show optimum performance as a semiconductor channel in an in-plane ferroelectric analogue synaptic device, whereas thicker films have a much poorer ferroelectric response due to screening effects by a higher concentration of charge carriers. The SnS ferroelectric device exhibits synaptic behaviors with highly stable room-temperature operation, high linearity in potentiation/depression, long retention, and low cycle-to-cycle/device-to-device variations. The simulated device based on ferroelectric SnS achieves ∼92.1% pattern recognition accuracy in an artificial neural network simulation. By switching the ferroelectric domains partially, multilevel conductance states and the conductance ratio can be obtained, achieving high pattern recognition accuracy.

Band‐tailored van der Waals heterostructure for multilevel memory and artificial synapse

“…PPF, an important role in STP, can be mimicked by stimulating the device with two identical pulses with a time interval Δ t . It describes the process wherein the temporal synaptic strength increases if the second pulse closely follows the previous one 45 . As shown in the inset of Figure 3(D), two successive pulses applied with a short Δ t can evoke a highly amplified EPSC response.…”

“…Furthermore, some important criteria, such as linear conductance modulation, high G max / G min ratio, and data levels, as well as low cycle‐to‐cycle/device‐to‐device variation, are essential to achieve an efficient ANN with high learning accuracy. The incremental voltage pulse scheme has been extensively adopted in many studies to optimize the linearity of LTP/LTD curve 45,50,51 . In this study, we also conducted the LTP/LTD measurement based on this varied voltage pulse scheme (potentiation: −5 to −7 V; depression: 5–8 V), while maintaining the P width (50 ms) and pulse interval (50 ms) at fixed values.…”

“…Furthermore, nonlinearity (|NL|) and effective number of states (NS eff ) under different numbers of pulses were evaluated to investigate the synaptic characteristics more quantitatively. The |NL| of the LTP and LTD curves can be extracted from the conductance ( G ) variation with the number of pulses by using the following equations 45,50 : where G p ( G d ) is the G of potentiation (depression), G min ( G max ) is the minimum (maximum) G , P max is the maximum number of pulses, and A p / A d is the linearity of potentiation/depression used to evaluate |NL|. The effective states are the states with Δ G above the noise range (defined as 0.5% of [ G max − G min ]) 49 .…”

Vortex‐Oriented Ferroelectric Domains in SnTe/PbTe Monolayer Lateral Heterostructures

“…With switchable spontaneous polarization, LHSs based on 2D ferroelectrics are naturally suitable for memories and low‐energy logic devices that can be easily tuned by external electric fields, such as edge‐contacted [ 29 ] or lateral [ 30 ] ferroelectric tunneling junctions and synaptic devices. [ 31 ] Nevertheless, despite the promising potential of applications, experimental studies of LHSs containing 2D ferroelectric materials—and the concomitant understanding of their interfacial tuning effects—are still rare. Here, we report the molecular beam epitaxial (MBE) growth and scanning tunneling microscopy (STM) characterization of the LHS between two distinct group‐IV monochalcogenide MLs—an in‐plane polarized ferroelectric SnTe ML and a paraelectric PbTe ML.…”

Ferroelectric Synaptic Transistor Network for Associative Memory

“…Performance of endurance (Figure 3g), compatibility for 3D integration (Figure 3h), energy consumption of every synaptic operation (Figure 3i) and spiking rate range (Figure 3j) of our device are compared with reported spike rate‐based artificial synapses that utilizing elements including CMOS circuits, [ 46 ] PEDOT, [ 48 ] WO x , [ 49 ] Ta 2 O 5− x , [ 50 ] SiO x N y :Ag, [ 15 ] STO, [ 51 ] Cu‐Pmssq, [ 52 ] AgInSbTe, [ 53 ] BaTiO 3 , [ 54 ] SnS [ 55 ] and HfO x . [ 56 ] Strikingly, our ferroelectric synaptic transistor is the only one that satisfies simultaneously all conditions including low‐energy consumption (less than 1 fJ, see note S1, Supporting Information), high fatigue durability (prior to 1 G), [ 25 ] compatibility for 3D integration and responsivity to spikes in brain‐like rate range.…”