Organic Field Effect Transistors II 2003
DOI: 10.1117/12.507630
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Influence of gate dielectrics on electrical properties of F8T2 polyfluorene thin film transistors

Abstract: The electrical properties of polymeric thin film transisitors (P-TFTs) based on poly(9,9-dioctylfluorene-cobithiophene) alternating copolymer (F8T2) have been studied. Device performance was compared for amorphous silicon nitride deposited by LPCVD and PECVD techniques, aluminum oxide deposited by sputtering, titanium oxide deposited by sputtering, and thermal silicon oxide gate dielectrics. A heavily n-type doped crystalline silicon wafer coated with the desired gate dielectric was used. Photolithographic pat… Show more

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Cited by 16 publications
(7 citation statements)
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“…F8T2 has been investigated by Swensen et al with various inorganic dielectrics to increase capacitance. The authors quoted mobility between 1 × 10 -5 and 5 × 10 -5 cm 2 V -1 s -1 for F8T2 devices without a “mobility-enhancing” monolayer at the semiconductor dielectric interface using the dielectrics TiO 2 and Al 2 O 3 , two different types of silicon nitride, and SiO 2 .…”
Section: Effects Related To the Gate Capacitance And Charge Densitymentioning
confidence: 99%
“…F8T2 has been investigated by Swensen et al with various inorganic dielectrics to increase capacitance. The authors quoted mobility between 1 × 10 -5 and 5 × 10 -5 cm 2 V -1 s -1 for F8T2 devices without a “mobility-enhancing” monolayer at the semiconductor dielectric interface using the dielectrics TiO 2 and Al 2 O 3 , two different types of silicon nitride, and SiO 2 .…”
Section: Effects Related To the Gate Capacitance And Charge Densitymentioning
confidence: 99%
“…The origin of the bias‐induced hysteresis in OFETs could be attributed to the use of ferroelectric materials as the gate dielectrics 9, 13. On the other hand, for OFETs made of non‐ferroelectric gate dielectrics, the origin of the bias‐induced hysteresis is correlated with the trapping of charge carriers in the gate dielectrics,14, 18 the interface at the active layer/dielectrics junction,19, 20 or the active layer21, 22 of devices. The trapped charges electrostatically shield the effective electrical bias applied to the gate with source/drain electrodes, in which the modulations of I D are associated with the trapping and de‐trapping processes of charge carriers23, 25 under the various bias regimes.…”
Section: Introductionmentioning
confidence: 99%
“…Previous studies have investigated the use of a number of materials for both the active layer and the gate dielectric in various TFT architectures. These efforts have highlighted the critical roles that interface effects, , material properties, , and processing play in determining device performance.…”
Section: Introductionmentioning
confidence: 99%