Inhibiting the Kink Effect and Hot-Carrier Stress Degradation Using Dual-Gate Low-Temperature Poly-Si TFTs

Chen, Hong-Chih; Tu, Hong-Yi; Huang, Hui‐Chun; Lai, Wei-Chih; Chang, Ting‐Chang; Huang, Shin-Ping; Tu, Yu‐Fa; Kuo, Chang-Hung; Zhou, Kuan‐Ju; Chen, Jianjie; Shih, Yu‐Shan; Chen, Guan-Fu; Su, Wan-Ching

doi:10.1109/led.2019.2951935

Cited by 13 publications

(4 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…[ 28–30 ] Under HCS operation, holes will be accelerated because of the large lateral electric field near the drain side, further becoming hot carriers to activate the generation of impact ionization that will result in degradation of the device performance. [ 31–33 ] However, as noted in Figure 4b, less HCS‐induced degradation is observed when the TFT adopts the stacked design. The time evolution of the threshold voltage shift (Δ V th ) and mobility variation (Δμ) also reveals that the proposed TFT has better HCS reliability than that of the conventional TFT, as shown in Figure 4c,d.…”

Section: Resultsmentioning

confidence: 96%

A Stacked p‐Type Low‐Temperature Polycrystalline Silicon Thin‐Film Transistor for Future Display Applications

Wang

Tai

Chang

et al. 2022

Adv Materials Technologies

Self Cite

View full text Add to dashboard Cite

In this study, a novel structural design of the p‐type low‐temperature polycrystalline silicon thin‐film transistors (p‐type LTPS TFTs) applied to the pixel structure of displays is proposed. Compared to the conventional pixel structure of displays, the proposed architecture can achieve the aperture ratio improvement by stacking the switch thin‐film transistor and the storage capacitor in a pixel region to enlarge the active space. Therefore, the demands of high‐resolution characteristics, such as a high aperture ratio, and high pixel densities for high‐end displays or novel technologies, can be satisfied by the adoption of the proposed design concept. Furthermore, the discussion of experimental and simulated results in terms of device physics of the transistor indicates that proposed TFTs possess higher performance and reliability properties. By modulating the geometry of the drain‐connected bottom metal in stacked TFTs, output characteristics and hot carrier phenomenon in devices can be further improved. Time‐dependent transfer characteristics, extracted electrical parameters, and numerical simulation results are performed to support our design.

show abstract

Section: Resultsmentioning

confidence: 96%

A Stacked p‐Type Low‐Temperature Polycrystalline Silicon Thin‐Film Transistor for Future Display Applications

Wang

Tai

Chang

et al. 2022

Adv Materials Technologies

Self Cite

View full text Add to dashboard Cite

show abstract

“…In the output characteristics, the saturation current abnormally increased in high drain-source voltage (V DS ). The increased saturation current was attributed to the kink effect [13]. When high V DS is applied to the LTPS TFTs, electron-hole pairs are generated by impact ionization and increase the saturation current by affecting the potential in the active layer.…”

Section: Electrical Characteristicsmentioning

confidence: 99%

Electrical-performance and reliability improvement of flexible low-temperature polycrystalline silicon thin-film transistors via post-annealing process

Im¹,

Ahn²,

Kim³

et al. 2022

Semicond. Sci. Technol.

View full text Add to dashboard Cite

We investigated the improvement methods of the electrical characteristics and reliability of flexible low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) by optimizing the annealing process. We investigated the effect of annealing on the device properties via electrical measurement and density-of-state (DOS) analysis. The annealing temperature should be reduced for flexible LTPS TFTs compared to rigid devices because the range of the thermal stability of flexible substrate is narrower than that of the glass substrate. As the activation annealing temperature (Ta) decreased, the threshold voltage and field-effect mobility (μFE) decreased, and the subthreshold swing (SS) increased. When the post-annealing temperature (Tpa) decreased, μFE increased, and the changes in the other parameters were negligible. The DOS decreased with an increase in Ta and a reduction in Tpa. These results originated from ineffective dopant activation and defect curing due to the lower Ta and the enhanced hydrogen defect passivation at the lower Tpa. Therefore, flexible LTPS TFTs with reduced Ta values exhibited similar μFE values and lower SS values when the post-annealing process was omitted. Furthermore, removing the post-annealing process improved the reliability of the flexible LTPS TFTs with reduced Ta values under electrical stress. According to a hot-carrier instability analysis, defect passivation by hydrogen was more stable than defect curing with a higher Ta. Consequently, although Ta was low for flexible LTPS TFTs, the electrical performance and reliability could be improved by optimizing the post-annealing process.

show abstract

“…-792mV -481mV PMOS 0.22/0.18 (µm) -832mV -507mV 2.2 Kink Effect When the bulk silicon MOSFET works at extremely low temperatures and the V DS is large enough, the I DS increases significantly, resulting in a KINK phenomenon in the output curve (Fig. 1a), which is particularly serious in NMOS [24,25,26,27]. This phenomenon can be physically explained by the freeze-out effect of substrate and impact ionization of carriers.…”

Section: Characteristics At Cryogenic Temperaturementioning

confidence: 99%

A cryogenic low power CMOS analog buffer at 4.2K

Huang

Luo

et al. 2021

IEICE Electron. Express

View full text Add to dashboard Cite

A novel power-efficient analog buffer at Liquid Helium Temperature (LHT) is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation based on SMIC 0.18µm CMOS technology show the high driving capability and low quiescent power consumption at cryogenic temperature. Operating at single 1.4 V supply, the circuit achieves a slew-rate of +36 V/µs and -33.8 V/µs for 10 pF capacitive load. The static power of the circuit is only 55.7µW.

show abstract

Inhibiting the Kink Effect and Hot-Carrier Stress Degradation Using Dual-Gate Low-Temperature Poly-Si TFTs

Cited by 13 publications

References 23 publications

A Stacked p‐Type Low‐Temperature Polycrystalline Silicon Thin‐Film Transistor for Future Display Applications

A Stacked p‐Type Low‐Temperature Polycrystalline Silicon Thin‐Film Transistor for Future Display Applications

Electrical-performance and reliability improvement of flexible low-temperature polycrystalline silicon thin-film transistors via post-annealing process

A cryogenic low power CMOS analog buffer at 4.2K

Contact Info

Product

Resources

About