Inserting scan at the behavioral level

Aktouf, Chouki; Fleury, Hervé; Robach, Chantal

doi:10.1109/54.867892

Cited by 14 publications

(5 citation statements)

References 11 publications

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“…Aktouf, et al proposed a method of scan insertion for functional RTL circuits 99) . In the method, sequential elements are stitched together in a random order in a functional RTL description so that scan paths are embedded in the circuit as a function of the circuit.…”

Section: Scan Based Methodsmentioning

confidence: 99%

Delay Testing: Improving Test Quality and Avoiding Over-testing

Kajihara

Ohtake

Yoneda

2011

IPSJ Transactions on System LSI Design Methodology

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Delay testing is one of key processes in production test to ensure high quality and high reliability for logic circuits. Test escape missing defective chips can be reduced by introducing delay testing. On the other hand, we need to concern yield loss caused by delay testing, i.e., over-testing. Many methods and techniques have been developed to solve problems on delay testing. In this paper, we introduce fundamental techniques of delay testing and survey recent problems and solutions. Especially we focus on techniques to enhance test quality, to avoid over-testing, and to make test design efficient by treating circuits described at register transfer level.

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Section: Scan Based Methodsmentioning

confidence: 99%

Delay Testing: Improving Test Quality and Avoiding Over-testing

Kajihara

Ohtake

Yoneda

2011

IPSJ Transactions on System LSI Design Methodology

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“…Since the object of this work is the second step of this whole process, we now restrict our attention to its first and third steps. This section is included mainly to make this article self-contained; for a more thorough presentation, the reader is referred to [6][7][8].…”

Section: Scan Insertion At the Rt-levelmentioning

confidence: 99%

“…There are many advantages to inserting scan at the RTL level like: benefiting from the synthesis process (i.e., better optimization in terms of area and timing), the ability to debug testability issues early in the design flow, and leveraging the optimization done by the synthesis tool. The possibility to insert scan at the RTL dates back to the late nineties [6][7][8]. Although this idea did not get a widespread attention in the meantime, an EDA tool that lets one do it, namely HiDFT-SIGNOFF by DeFacTo Technologies, has appeared and is commercially available.…”

Section: Introductionmentioning

confidence: 99%

“…This may be one reason why in that case, the reoptimization possibility is commonly dropped, in favour of a single optimization at the time of insertion. Most studies on higher-level scan either do not mention optimization [7], or mention local optimizations only, meaning trying to reuse bits of functional paths for the scan path, thus reducing the need for added nets and additional multiplexing logic [6,[16][17][18]. In [8] an attempt is made to achieve both local and global optimizations by carefully delineating a graphic model for the scan ordering problem.…”

Section: Introductionmentioning

confidence: 99%

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A Graph‐Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions

Zaourar

Kieffer

Aktouf³

2012

VLSI Design

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The scan chain insertion problem is one of the mandatory logic insertion design tasks. The scanning of designs is a very efficient way of improving their testability. But it does impact size and performance, depending on the stitching ordering of the scan chain. In this paper, we propose a graph-based approach to a stitching algorithm for automatic and optimal scan chain insertion at the RTL. Our method is divided into two main steps. The first one builds graph models for inferring logical proximity information from the design, and then the second one uses classic approximation algorithms for the traveling salesman problem to determine the best scan-stitching ordering. We show how this algorithm allows the decrease of the cost of both scan analysis and implementation, by measuring total wirelength on placed and routed benchmark designs, both academic and industrial.

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“…First, fault models talk about gate-level entities; so inserting logic to detect such faults at higher-level is counterintuitive. But it is feasible as demonstrated in [1], [2] and [3]. An example of RTL code modification to include scan is given in Fig.…”

Section: Introductionmentioning

confidence: 99%