Insights and Advances on the Design of CMOS <i>Sinh</i> Companding Filters

Katsiamis, Andreas G.; Glaros, K. N.; Drakakis, E.M.

doi:10.1109/tcsi.2008.921037

Cited by 38 publications

(33 citation statements)

References 25 publications

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“…whereˆ IN+ ,ˆ IN− are the positive and negative input voltages, I bias is the bias current, n is the subthreshold slope factor, and V T ( ∼ =26 mV) is the thermal voltage [4,5]. Thus, the left side uppermost S+ cell in Fig.…”

Section: Proposed Configurationmentioning

confidence: 99%

“…According to (5), the output current is independent of the bias current I a of the splitter. This is an important conclusion, not mentioned in [4] where all transconductors are biased at the same current I o , and it will be used for reducing the power dissipation of the multiplier by choosing I a < I o instead of I a = I o as in [4].…”

Section: Proposed Configurationmentioning

confidence: 99%

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0.65V class-AB current-mode four-quadrant multiplier with reduced power dissipation

Kasimis

Psychalinos

2011

AEU - International Journal of Electronics and Communications

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Section: Proposed Configurationmentioning

confidence: 99%

Section: Proposed Configurationmentioning

confidence: 99%

0.65V class-AB current-mode four-quadrant multiplier with reduced power dissipation

Kasimis

Psychalinos

2011

AEU - International Journal of Electronics and Communications

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“…2c and d, respectively. This approach employs complementary devices to implement the same translinear loop equation and thus suffers from different subthreshold slopes owing to the body effect of the NMOS devices, something which is unavoidable in standard CMOS processes [4]. Hence, we choose the circuits in Figs.…”

Section: Fig 1 Current Multiplier Block Diagrammentioning

confidence: 99%

Ultra-low-power, class-AB, CMOS four-quadrant current multiplier

Sawigun

Serdijn

2009

Electron. Lett.

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A class-AB four-quadrant current multiplier constituted by a class-AB current amplifier and a current splitter which can handle input signals in excess of ten times the bias current is presented. The proposed circuit operation is based on the exponential characteristic of BJTs or subthreshold MOSFETs. The multiplier is designed using the latter devices and achieves very low power consumption. Simulation results show that from a 0.65 V supply, the proposed circuit consumes 12.4 nW static power while less than 230 dB total harmonic distortion is achieved for an input modulation index up to 10.Introduction: Based on the well-known exponential characteristics of BJTs or weak inversion MOSFETs, four-quadrant current multiplier circuits have been designed from different principles, e.g. transconductor/ conveyor based [1] and translinear circuit based [2] current multipliers. Most of them are restricted to class-A operation that does not allow the input signals' swing to become higher than their bias currents.In this Letter, a fully class-AB four-quadrant analogue current multiplier is presented. The proposed multiplier is formed by a dual output current amplifier which is biased by controlled currents generated from a current splitter. Both the amplifier and splitter circuits can be realised from the same basic circuit block, called Sinh transconductor, which provides class-AB operation. Therefore, fully class-AB multiplication is obtained. Owing to the class-AB operation, the multiplier circuit can be designed to process high input signal amplitudes while its bias current can be kept low. Circuit simulation using a 0.13 mm model parameter shows that, for a 0.5 nA bias current, input currents with amplitudes of 5 nA can be applied to the circuit and good fourquadrant multiplication is performed.

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“…The resulting compressed output voltage is then expanded and simultaneously converted into a linear current. In sinh-domain filtering, the compression of the input current could be performed by the inverse of the hyperbolic sine function, realized by translinear loops formed by bipolar transistors in an active region or metal-oxide semiconductor (MOS) transistors in a weak inversion [5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

A low-voltage and low-power sinh-domain universal biquadratic filter for low-frequency applications

Khanday¹,

Shah²

2013

Turk J Elec Eng & Comp Sci

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Sinh-domain CMOS filters have favorable properties, such as a wide dynamic range at low supply voltage, compactness, linearity, and low power consumption. These properties are becoming increasingly important for biomedical applications that require extremely low-power dissipation and neuromorphic circuits that attempt to reproduce the biophysics of biological neurons and synapses. In this paper, a low-voltage sinh-domain universal biquadratic filter circuit is introduced. The circuit, aside from permitting the independent adjustment of pole frequency ( ω0) and the quality factor (Q), is free from matching conditions, capable of absorbing the shunt parasitic capacitances, amenable for monolithic integration, and composed of merely a few transconductor cells and grounded elements. The other features of the circuit are its low sensitivity and good linearity. Simulated results are obtained to prove the theoretical analyses and the filter shows a dynamic range of 59.17 dB and power consumption of only 19.2 nW.

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Insights and Advances on the Design of CMOS Sinh Companding Filters

Cited by 38 publications

References 25 publications

0.65V class-AB current-mode four-quadrant multiplier with reduced power dissipation

0.65V class-AB current-mode four-quadrant multiplier with reduced power dissipation

Ultra-low-power, class-AB, CMOS four-quadrant current multiplier

A low-voltage and low-power sinh-domain universal biquadratic filter for low-frequency applications

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