Integrate-and-Fire Neuron Circuit With Synaptic Off-Current Blocking Operation

Abstract

In this study, we propose an analog CMOS integrate-and-fire (I & F) neuron circuit with a synaptic off-state current blocking operation. The proposed circuit prevents unintended potential changes in the membrane capacitor owing to the off-state current of synaptic devices, thereby preventing a decrease in the accuracy of the spiking neural network (SNN) inference system. Compared to the conventional I & F neuron circuit, the basic I & F and synaptic off-current blocking operations of the proposed I & F neuron circuit were confirmed in a circuit-level simulation. Furthermore, to verify the effect of the proposed circuit on the neural network, a multi-layer SNN simulation was performed, and the accuracy of the inference system was compared for the conventional and proposed I & F neuron circuits. The simulation and analysis results demonstrate the robustness of the I & F neuron circuit to the drop in accuracy of inference systems due to off-state currents in synaptic devices. INDEX TERMS neuromorphic system, CMOS-based integrate-and-fire (I & F) neuron circuit, spiking neural networks (SNNs), synaptic off-state current blocking operation, TCAD simulation, SPICE simulation, SNN high-level simulation.

A Compact Integrate-and-Fire Neuron Circuit Embedding Operational Transconductance Amplifier for Fidelity Enhancement

“…The most striking similarity of the advanced computing architecture to the human brain calls for area efficiency, low power consumption, and a low training cost for realizing the extreme parallelism in massive data processing [18], [19]. For this goal, a more hardware-oriented spiking neural network (SNN) supported by I&F neuron circuits and synapse arrays are considered a plausible solution that enables event-driven computing [20], [21], [22], [23]. The mathematical and symbolic representations of the functions of neuron circuits and synaptic devices are schematically shown in Figs.…”