Integrated chip-scale simulation of pattern dependencies in copper electroplating and copper chemical mechanical polishing processes

Tugbawa, Tamba; Park, T.H.; Boning, Duane S.

doi:10.1109/iitc.2002.1014922

Cited by 23 publications

(25 citation statements)

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“…Commercial CMP simulation software is available from companies such as Praesagus [9]. In our current implementation, we use a CMP simulation model derived from the Ph.D. thesis of Tugbawa [10]. The results we describe here have been previously reported at PMJ-2005 [2].…”

Section: A Topography-aware Optical Proximity Correctionsupporting

confidence: 70%

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Kahng

Liu

Wang

2005 International Conference on Computer Design

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In leading-edge chip designs, the dimensional variation that arises from lithography, etch, and planarization processes of multilevel metallization is significant due to its direct impact on wire parasitics and circuit timing. Modeling the dimensional variation helps reduce uncertainty in the extraction of parasitics and enables closure -not only of design, but of various process-design tradeoffs. Today, interconnect analyses and manufacturing are complicated by several close interactions among various components of the design and manufacturing flows. Our research program explores many of these previously-ignored, cross-domain interactions for multilevel interconnect, including those between lithography, topography, dummy fill, and circuit performance. Studies described in this paper include wire CD control through topography-aware OPC; accurate parasitic extraction by modeling wire sidewall angle and dummy fill; and timing-driven, intelligent CMP fill synthesis.

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Section: A Topography-aware Optical Proximity Correctionsupporting

confidence: 70%

Supply voltage degradation aware analytical placement

Kahng

Liu

Wang

2005 International Conference on Computer Design

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“…In copper CMP, overpolishing is defined as polishing beyond the time it takes to remove the overburden copper and barrier at any spatial location. During the overpolishing stage, the dielectric is eroded [64].…”

Section: ) Oxide Cmpmentioning

confidence: 99%

“…Finally, copper, barrier, and dielectric are polished at the same time. As stated in [64], to model a copper-CMP process, three stages of polish are identified: excess-copper removal, barrier-film removal, and overpolish stage, as shown in Fig. 12.…”

Section: ) Oxide Cmpmentioning

confidence: 99%

“…This is required to prevent electrical connection between adjacent interconnect lines. Due to the heterogeneous nature of copper CMP, a specific set of process parameters, as well as a consumable set, are required to achieve the particular removal rate for each corresponding material [64].…”

Section: ) Oxide Cmpmentioning

confidence: 99%

“…In computing the amount of dishing during the overpolish stage, the dishing that occurs during the barrier-clearing stage is used as an initial condition. It is important to note that the term overpolishing is used loosely in the CMP literature, and in the CMP industry [64]. [27] propose the first minvariation formulation using an LP approach.…”

Section: ) Oxide Cmpmentioning

confidence: 99%

See 2 more Smart Citations

Detailed Placement for Enhanced Control of Resist and Etch CDs

Gupta

Kahng

Park³

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-We survey recent research and practice in the area of chemical-mechanical polishing (CMP) fill synthesis, in terms of both problem formulations and solution approaches. We review the CMP as the planarization technique of choice for multilevel very large-scale integration metallization processes. Post-CMP wafer topography varies according to pattern density. We review density-analysis methods and density-control objectives that are used in today's fill-synthesis algorithms. In addition, we discuss the concept of design-driven fill synthesis that seeks to optimize CMP fill with respect to objectives beyond mere density uniformity. Design-driven fill synthesis minimizes the impact of CMP fill on design performance and parametric yield while still satisfying the density criteria that are motivated by manufacturing models. We conclude with a discussion of where CMP fill synthesis may be naturally integrated within future design and manufacturing flows.Index Terms-Chemical-mechanical polishing (CMP), CMP fill, design-driven fill, topography.

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Chemical Mechanical Planarization: Slurry Chemistry, Materials, and Mechanisms

Krishnan¹,

Nalaskowski²,

Cook³

2009

Chem. Rev.

409

271

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Mahadevaiyer Krishnan received his Ph.D. degree in Physical Chemistry/ Electrochemistry from Georgetown University under the direction of Prof. Robert de Levie. He was a postdoctoral fellow under Prof. A. J. Bard in the University of Texas at Austin. He joined the IBM T. J. Watson Research Center at Yorktown Heights in 1984 as a research scientist. Krishnan's research interests include interfacial electrochemistry, colloid and surface science, and semiconductor process development. He has been leading research and development as well as manufacturing implementation of CMP slurries and processes in IBM since 1994.

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Integrated chip-scale simulation of pattern dependencies in copper electroplating and copper chemical mechanical polishing processes

Cited by 23 publications

References 1 publication

Supply voltage degradation aware analytical placement

Supply voltage degradation aware analytical placement

Detailed Placement for Enhanced Control of Resist and Etch CDs

Chemical Mechanical Planarization: Slurry Chemistry, Materials, and Mechanisms

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