Integration challenges of copper Through Silicon Via (TSV) metallization for 3D-stacked IC integration

Olmen, J. Van; Huyghebaert, Cedric; Coenen, Jan; Aelst, J. Van; Sleeckx, Erik; Ammel, A. Van; Armini, Silvia; Katti, Guruprasad; Vaes, Jan; Dehaene, Wim; Beyne, Eric; Travaly, Youssef

doi:10.1016/j.mee.2010.06.026

Cited by 70 publications

(29 citation statements)

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“…In chip level development, Damascene Cu interconnect technique [1] has gradually replaced traditional aluminum (Al) to improve electromigration (EM) resistance, so as to sustain high-level current impact in advanced microelectronics. The trends of portability, wearability, and multifunctionality have also pushed the microelectronic industry to develop ultrafine pitch and high-density interconnections, in which through-silicon-via (TSV) [2,3] is a promising technique to reach the goal. In TSV technology, Cu is used to fill the via as an interconnect.…”

Section: Introductionmentioning

confidence: 99%

Impurity Effects in Electroplated-Copper Solder Joints

Lee

Chen

2018

Metals

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Copper (Cu) electroplating is a mature technology, and has been extensively applied in microelectronic industry. With the development of advanced microelectronic packaging, Cu electroplating encounters new challenges for atomic deposition on a non-planar substrate and to deliver good throwing power and uniform deposit properties in a high-aspect-ratio trench. The use of organic additives plays an important role in modulating the atomic deposition to achieve successful metallic coverage and filling, which strongly relies on the adsorptive and chemical interactions among additives on the surface of growing film. However, the adsorptive characteristic of organic additives inevitably results in an incorporation of additive-derived impurities in the electroplated Cu film. The incorporation of high-level impurities originating from the use of polyethylene glycol (PEG) and chlorine ions significantly affects the microstructural evolution of the electroplated Cu film, and the electroplated-Cu solder joints, leading to the formation of undesired voids at the joint interface. However, the addition of bis(3-sulfopropyl) disulfide (SPS) with a critical concentration suppresses the impurity incorporation and the void formation. In this article, relevant studies were reviewed, and the focus was placed on the effects of additive formula and plating parameters on the impurity incorporation in the electroplated Cu film, and the void formation in the solder joints.

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Section: Introductionmentioning

confidence: 99%

Impurity Effects in Electroplated-Copper Solder Joints

Lee

Chen

2018

Metals

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“…Via extrusion, or pop-up, is a reliability issue in 3D integration in which Cu extrudes from the wafer surface to damage the interconnect structures above the vias [5]. A previous study has shown that stress-induced interfacial delamination could result in via extrusion [7].…”

Section: Local Plasticity and Via Extrusionmentioning

confidence: 99%

“…In addition, strain hardening may accompany plasticity to raise the yield strength locally near the top of the Cu via [21]. With stabilized grain structure and strain hardening, when the TSV is subjected to subsequent processing at temperatures lower than T m , the plasticity in the via is limited to minimize further via extrusion [5,6].…”

Section: Local Plasticity and Via Extrusionmentioning

confidence: 99%

“…Thermal stresses can arise during fabrication, testing and operation of the TSV structures due to the large mismatch in the coefficient of thermal expansion (CTE) between Cu and Si. The stresses are large enough to cause serious reliability concerns even structural failures in the integrated structure, including TSV extrusion, cracking of Si near the TSV and degradation of device performance [5][6][7][8][9]. Management and mitigation of thermal stresses in the TSV structures require proper stress characterization and modeling analysis.…”

Section: Introductionmentioning

confidence: 99%

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Characterization of thermal stresses and plasticity in through-silicon via structures for three-dimensional integration

Jiang

Ryu

et al. 2014

AIP Conference Proceedings

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“…They are also compatible with both surface mounting and vertical 3D chip stacking approaches, which result in a high device density and more compact packaging. Various methods for fabricating TSVs have being developed [14], such as Cu electroplating [15,16,17], bottom-up Cu electroplating [18] and molten solder filling [19]. Because of its low resistivity, Cu is an attractive filling material.…”

Section: Introductionmentioning

confidence: 99%

Millimeter-wave transmission line with through-silicon via for RF-MEMS devices

Ogawa

Yuasa

Fujii

et al. 2013

IEICE Electron. Express

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Abstract:We designed and fabricated a low-loss transmission line structure with through-silicon vias (TSVs) for use in the millimeterwave region for three-dimensional packaging of radio frequency microelectromechanical system devices. High-frequency simulations were used to determine the optimum transmission line structure. A transformer was employed to compensate for the impedance mismatch between the TSVs and the coplanar waveguide. The proposed structure was fabricated using a combination of surface micromachining and the molten solder ejection method. The electrical properties of the TSVs and the transmission line were measured, and a low insertion loss of 0.7 dB at 80 GHz was achieved.

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Integration challenges of copper Through Silicon Via (TSV) metallization for 3D-stacked IC integration

Cited by 70 publications

References 0 publications

Impurity Effects in Electroplated-Copper Solder Joints

Impurity Effects in Electroplated-Copper Solder Joints

Characterization of thermal stresses and plasticity in through-silicon via structures for three-dimensional integration

Millimeter-wave transmission line with through-silicon via for RF-MEMS devices

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