Integration of InGaAs Channel n-MOS Devices on 200mm Si Wafers Using the Aspect-Ratio-Trapping Technique

Abstract

We report on the fabrication on InGaAs/InP implant free quantum well (IFQW) n-MOSFET devices on 200mm wafers in a Si CMOS processing environment. The starting virtual InP substrates were prepared by means of the aspect-ratio-trapping technique. Post CMP these substrate resulted in a planar substrate with a rms roughness of 0.32 nm. After channel and gate processing source drain regions were formed by the selective epitaxial growth of Si doped InGaAs. Contact to the source/drain regions was made by a standard W-plug/metal 1 process. The contact resistance was estimated to be on the order of 7x10 -7 Ω.cm 2 . Fully processed devices clearly showed gate modulation albeit on top of high levels of source to drain leakage. The source of this leakage was determined to be the result of the unintentional background doping of the InP buffer layer. Simulations show that the inclusion of the p-InAlAs between the InP and InGaAs can effectively suppress this leakage. This development is a significant step towards the integration of InGaAs based devices on a standard CMOS platform.

(Invited) Stress Techniques in Advanced Transistor Architectures: Bulk FinFETs and Implant-Free Quantum Well Transistors

“…A pFET version has been demonstrated in the Si/Ge material system, Figure 1. For nFETs, the Ge concentration in the channel needs to be lower than the substrate concentration to get the desired conduction band offset: in this case a structure with a Si 1-x Ge x -channel on a Si 1-y Ge y Strain-Relaxed Buffer (SRB) can be imagined (x<y), besides various solutions in the III/V material systems (10)(11)(12). IFQW pFETs show excellent performance and electrostatics (14)(15)(16).…”

Heteroepitaxy of InP on Si(001) by selective-area metal organic vapor-phase epitaxy in sub-50 nm width trenches: The role of the nucleation layer and the recess engineering

“…The indium gallium arsenide compound semiconductor, with high Indium concentration has been considered as a candidate for nchannel MOS devices beyond 10 nm node technology due to its intrinsically superior electron mobility, high saturation velocity and proper optical bandgap. [3][4][5] The best option for the growth of such a complex ternary compound would be to make use of InP binary compounds as a buffer for the lattice matched In 0.53 Ga 0.47 As channel. [6][7][8] Nevertheless, for the integration of III-V compounds on Si substrates, many issues still need to be overcome such as the lattice mismatch (f InP/Si ¼ 8.06%) as well as the polar/non-polar interfaces resulting in the generation of crystalline defects in high density: misfit and threading dislocations, twins, stacking faults, anti-phase boundaries, which would strongly degrade the device performances.…”

Monitoring defects in III–V materials: A nanoscale CAFM study

“…Finally, a preliminary analysis of a patterned sample fabricated using Aspect Ratio Trapping (ART) approach [18,19] was performed. In this fabrication method, threading dislocations are confined within high aspect ratio sub-micron trenches that prevents TDs from reaching the surface of III-V materials.…”