-Each year tens of billions of Dollars are wasted by the microelectronics industry because of missed deadlines and delayed design projects. These delays are partially due to design iterations many of which could have been avoided if the low level ramifications of high level design decisions, at the Architecture-and Algorithmic-level would have been known before the time consuming and tedious RT-and lower level implementation started. In this contribution we present a System-level design flow and respective EDA support tools for low power designs. We analyze the requirements for such a design technology, which shifts more responsibility to the system architect. We exemplify this approach with a design flow for low power systems. The architecture of an Algorithm-level power estimation tool will be presented together with some use cases based on an EDA product which has been commercially developed from the research results of several collaborative projects funded by the Commission of the European Community.
I IntroductionAccording to [1] 85% of all design projects finish late if they finish at all. The same source states that all projects are late by 53% of the originally estimated design time. Gartner/Dataquest [2] reported about the number of design iterations and the design time. From these data we can estimate the average design time for current designs to be some 10 months, the expected design time for next designs to be like 15 months. We can also estimate from this report that an average of 4.7 design iterations is needed to complete a design. Our conclusion is that NRE cost are not determined by the increasing mask cost, but rather by the design c ost, secondly that the design community is obviously pessimistic with regard to the design efforts for new designs and thirdly that the design cost could be significantly reduced if design iterations could be avoided.If we assume that the average employment cost for a design engineer in high cost regions is some US$ 200k and if we further expect an additional cost of US$ 30 k for EDA licenses, about 1/3 rd of the total design cost or some US$ 70 k per design engineer are spent due to unexpected design iterations. These are typically due to late detection of design errors or because design problems are found at a very late stage of the design process. Even worse, these delays often cause missed market opportunities if competition is able to enter the market earlier and gains large market shares during the most profitable market window. A delay in market entry of six months can result in reduced revenues of up to 50%. In conclusion, delays and unnecessary design iterations cost the industry tens of billions of Dollars each year.The reasons for the large number of design iterations are manifold: less predictable semiconductor fabrication processes, more aspects to be considered, complexity of the designs. However, there is one common issue between these reasons: The problems are detected too late! Months of tedious design time had already been spent and many...
