System-level power optimization

Nebel, Wolfgang

doi:10.1109/dsd.2004.1333255

Cited by 8 publications

(1 citation statement)

References 12 publications

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“…Designers today must evaluate various power optimizations as early as possible in an electronic system level (ESL) design flow, since design changes are easier and have the greatest impact on application power dissipation at the system level [1]- [2]. In order to explore these optimizations, accurate power estimation models are necessary.…”

Section: Introductionmentioning

confidence: 99%

Methodology for multi-granularity embedded processor power model generation for an ESL design flow

Park

Pasricha

Kurdahi

et al. 2008

Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is critical for these processor power models to be useable across various modeling abstractions in an electronic system level (ESL) design flow, to guide early design decisions. In this paper, we propose a unified processor power modeling methodology for the creation of power models at multiple granularity levels that can be quickly mapped to an ESL design flow. Our experimental results based on applying the proposed methodology on an OpenRISC processor demonstrate the usefulness of having multiple power models. The generated models range from very high-level two-state and architectural/ISS models that can be used in transaction level models (TLM), to extremely detailed cycle-accurate models that enable early exploration of power optimization techniques. These models offer a designer tremendous flexibility to trade off estimation accuracy with estimation/simulation effort.

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Section: Introductionmentioning

confidence: 99%