Interconnect opportunities for gigascale integration

Meindl, J.D.; Davis, Jeffrey A.; Zarkesh-Ha, Payman; Patel, C.S.; Martin, K. P.; Kohl, Paul A.

doi:10.1147/rd.462.0245

Cited by 160 publications

(71 citation statements)

References 40 publications

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“…Three-dimensional integrated circuit (3D IC) technology has recently attracted considerable interest as a "More-than-Moore" solution [1,2]. The through silicon via (TSV) is a key component of 3D ICs; it offers decreased latency, decreased energy-per-bit, and increased bandwidth density [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

High-aspect ratio through-silicon vias for the integration of microfluidic cooling with 3D microsystems

Hong

et al. 2015

Microelectronic Engineering

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Section: Introductionmentioning

confidence: 99%

High-aspect ratio through-silicon vias for the integration of microfluidic cooling with 3D microsystems

Hong

et al. 2015

Microelectronic Engineering

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“…But delay associated with interconnects are becoming increasingly important with advancement of technology levels. This is because in deep submicron technologies, interconnect can no longer be seen as simple resistor but the associated parasitic such as capacitance and inductance also need to be considered [1]. This increasing interconnects delay leads the researchers to find an alternative material for future global VLSI interconnects.…”

Section: Introductionmentioning

confidence: 99%

Analysis of mixed CNT bundle interconnects: Impact on delay and power dissipation

Majumder

Kaushik

Manhas

2012

2012 5th International Conference on Computers and Devices for Communication (CODEC)

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This research paper proposes a hierarchical modelling approach for mixed carbon nanotube (CNT) bundle (MCB) interconnects. Based on the arrangements of single-walled CNTs (SWCNT) and multi-walled CNTs (MWCNTs), three different MCB structures are proposed. Transient analysis is performed for bundled CNT structures to address the effect of propagation delay and power dissipation. It has been observed that the delay and power dissipation are significantly improved for the proposed MCB structures as compared to bundled SWCNT and bundled MWCNT at different global interconnect lengths.

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“…Interconnects are now a key factor determining overall IC performance [2] and are analogously affected, through line edge roughness (LER). The causes of LER are well understood, arising T.D.…”

Section: Introductionmentioning

confidence: 99%

Capacitance variability of short range interconnects

et al. 2007

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End of the roadmap integrated circuit interconnects suffer from capacitance variability due to line edge roughness (LER), significantly impacting overall circuit performance. We forecast the capacitance variability of short range interconnects with realistic line edge roughness at the upcoming 45, 32, and 22 nm technology nodes using a fast TCAD capacitance tool. Capacitance variability is layout sensitive and worsens with reduction in feature size, and together with the increasing device variability requires inclusion in statistical models of standard cells from the 45 nm node onwards. If LER does not improve then, for example, by the 22 nm node, short parallel lines on metal 1 are predicted to have 12% variability and, depending on layout, SRAM bit line capacitance 7% variability.

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Interconnect opportunities for gigascale integration

Cited by 160 publications

References 40 publications

High-aspect ratio through-silicon vias for the integration of microfluidic cooling with 3D microsystems

High-aspect ratio through-silicon vias for the integration of microfluidic cooling with 3D microsystems

Analysis of mixed CNT bundle interconnects: Impact on delay and power dissipation

Capacitance variability of short range interconnects

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