Intrinsic Variability and Reliability in Nano-CMOS

Abstract

Intrinsic device variability and reliability, such as dopant and geometry fluctuations, as well as temporal degradation, poses a fundamental challenge to CMOS scaling and IC design. Their importance is rapidly increasing as device feature size approaches the atom dimension. Predictive modeling helps benchmark its impact on circuit performance, indicating the trend, priority and techniques of variability control. Furthermore, statistical interaction between static variation and temporal shift is investigated.

A Unified Approach for Performance Degradation Analysis from Transistor to Gate Level

“…∆H represents the minimum possible magnitude of OTF, that is the height of one silicon atom layer which is equal to 2.71Å. The correlation length λ of OTF typically ranges between 1-3nm, as reported in [4].…”

“…• The E. Maricau [7] and Yu Cao [4][9] models are used for the Oxide Thickness Fluctuation (OTF), Random Dopant Fluctuation (RDF) and Hot-carrier-Instability (HCI), to evaluate the variation of threshold voltage (V th ) and mobility (µ). The consequent change in the drive current (I on ) are evaluated.…”

“…Because of lower doping concentration, addition or deletion of a few impurity atoms can significantly change transistor properties, especially the V th . The physics based model, as stated in [4] is given by:…”

“…As V th is directly proportional to gate oxide thickness T ox , any fluctuation in oxide thickness leads to change in V th . This effect is even more highlighted when the gate oxide thickness approaches atomic dimensions [4]. The threshold voltage variation due to oxide thickness fluctuation can be expressed as:…”

“…A single chip can house billions of transistors [3]. Scaling at such a fast pace eventually leads to increased variability and reliability issues, that pose a unique challenge for circuit lifetime estimation [4].…”