Despite intensive attention on line-edge roughness (LER), contact-edge roughness (CER) has been relatively less studied. Contact patterning is one of the critical steps in a state of the art lithography process; meanwhile, design rule shrinking leads to larger CER in contact holes. Since source/drain (S/D) contact resistance depends on contact area and shape, larger CER results in significant change in a device current. We first propose a CER model based on the power spectral density function, which is a function of rms edge roughness, correlation length, and fractal dimension. Then, we present a comprehensive contact extraction methodology for analyzing process-induced CER effects on circuit performance. In our new contact extraction model, we first dissect the contact with a same distance, and then calculate the effective resistance considering both the shape weighting factor and the distance weighting factor for stress-induced complementary metal-oxide semiconductor (CMOS) cells. Using the results of CER, we analyze the impact of both random CER and systematic variation on the S/D contact resistance, and the device saturation current. Results show that the S/D contact resistance and the device saturation current can vary by as much as 135.7 and 4.9%, respectively. C 2010 Society of Photo-Optical Instrumentation Engineers. Downloaded From: http://nanolithography.spiedigitallibrary.org/ on 05/22/2014 Terms of Use: http://spiedl.org/terms computer science from University of California, Los Angeles, in 2000. He is currently an associate professor and director of the UT Design Automation (UTDA) Laboratory, Department of Electrical and Computer Engineering, University of Texas at Austin. He has published more than 120 refereed papers in international conferences and journals, and is the holder of eight U.S. patents. His research interests include nanometer VLSI physical design, design for manufacturing, vertical integration of technology, design and architecture, and design/CAD for emerging technologies.