Investigating Series and Parallel Oxide Memtransistors for Tunable Weight Update Properties

Abstract

Currently, analog in-memory computing, employing memristors into a crossbar array architecture (CAA), is the leading system among available neuromorphic hardware. This study presents a highly tunable synaptic weight update based on a multiterminal memtransistor device as a solution for nonlinear synaptic operations and crosstalk issues in CAA memristors, which are long-standing challenges in neuromorphic hardware applications. To explore an effective device structure for tunable weight update properties, a memtransistor device with a series and parallel structure functioning by interface type and oxygen migration is fabricated using a ZnO channel layer and an amorphous TiO2 memristor. The series memtransistor device exhibits a significant tunable weight update property at the gate knob; thus, it simultaneously can function as a selector (accelerating and inhibiting weight update) in the CAA and tune and ultimately improve the linearity of the potentiation and depression curves. Neuromorphic hardware based on tunable synaptic weight update functions provides advantageous features for accuracy and crosstalk issues. Using the Fashion-MNIST pattern recognition simulation, the tuned weight update properties are obtained by three different write and read condition combinations, and the results are close to ideal accuracy.

High-Reliability and Self-Rectifying Alkali Ion Memristor through Bottom Electrode Design and Dopant Incorporation

“…The nonlinearity and asymmetry of the LTP/LTD and the accuracy (%) obtained by each device for Digit and Fashion MNIST are summarized in Table S1. As is well-known, the linearity and symmetry of the weight update are the most important factors determining the accuracy of neuromorphic hardware . As a result, the Al 6 device with the highest symmetry and linearity has the highest recognition rate.…”

“…The resistive switching (RS) characteristics resulting from the state change of materials, including ionic memristor, ferroelectric tunnel junction (FTJ), phase-change memory, and magnetic tunnel junction (MTJ), have been considered promising candidates as next-generation nonvolatile memories (NVMs). − They have in common the characteristic to express nonvolatile multi-bit (or analog) resistance states, depending on the magnitude, duration time, and number of programming pulses, used in a two-terminal structure, enabling them to be utilized as synapse devices in neuromorphic hardware. The matrix-vector multiplier using memristors with a crossbar-array architecture (CAA) is the foremost scheme for chip implementation (analog accelerator) of artificial neural networks (ANNs). − Among the promising memristors, the ionic memristor is particularly suited for neuromorphic and analog computation in terms of switching speed, simple structure (metal/insulator/metal), availability of various materials (transition metal oxides, TMOs), and multi-bit capability (larger on/off ratio). − However, long-standing issues such as the sneak current issue in CAA and reliability issues (such as device-to-device and cycle-to-cycle variation) caused by the RS mechanism “defect control” have hindered neuromorphic hardware implementation. − …”

“…This characteristic is due to the fact that the resistance change behavior occurs within a very small filament, resulting in a large amount of current passing through the narrow filament and a fast switching speed. In the past, filament-type memristors have been mainstream for NVM (resistive RAM) applications that require only 1-bit implementation, − but recently, interface-type memristor devices that exhibit gradual switching characteristics have attracted attention in neuromorphic hardware applications that require multi-bit implementation. ,,,, Since filament-type memristors have difficulty controlling filament formation and ensuring uniformity, the device-to-device and cycle-to-cycle variation is larger than that of interface-type memristors. In addition, because they exhibit an Ohmic conduction regime in the low-resistance state (LRS), a cell selector such as a transistor or ovonic threshold switching (OTS) device is essential to avoid errors caused by the sneak current in the CAA. − Filament-type memristors, which typically demand operating currents of the mA range for programming, require a relatively large channel of transistors for a cell selector, which is disadvantageous in terms of integration.…”

Carrier Type Exchange with the Sweep Direction in a WORM Memory Device

“…Recently, potential prospects for future-oriented data storage uses have surfaced in the shape of organic-based resistive memory resources, opening up new avenues for the development of efficient organic electronics. Research on the preparation and characterization of resistive memory using organic materials and nanocomposites is a current-day hot topic due to easy availability, reusability, high stability, and high efficiency. − …”

“…Because of its benefits of convenience and versatility, resistive switching memory is now a potential candidate for future-oriented data storage technology for many of its diverse applications. − Additionally, resistive memory has an enormous amount of opportunity for implementing large storage ability, quick data transmission, rapid retrieval, minimal power usage, and neuromorphic computing. This can fulfill the essential criteria for forthcoming UHDDS electronics and artificial intelligence innovations. − A potential successor of our current technology must not only fulfill the same expectations as CMOS but also outperform prevalent technology in at least a number of several clue aspects, including power consumption, mass production, fabrication costs, and performance, and overcome current functionalities . These efforts are being made from a multidisciplinary point of view, for which the contribution of physicists, chemists, and engineers is essential for overcoming the enormous challenges ahead.…”