Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test

Abstract

On-chip power-rail electrostatic discharge (ESD) protection circuit designed with active ESD detection function is the key role to significantly improve ESD robustness of CMOS integrated circuits (ICs). Four power-rail ESD clamp circuits with different ESD-transient detection circuits were fabricated in a 0.18-m CMOS process and tested to compare their system-level ESD susceptibility, which are named as power-rail ESD clamp circuits with typical RC-based detection, PMOS feedback, NMOS+PMOS feedback, and cascaded PMOS feedback in this work. During the system-level ESD test, where the ICs in a system have been powered up, the feedback loop used in the power-rail ESD clamp circuits provides the lock function to keep the ESD-clamping NMOS in a "latch-on" state. The latch-on ESD-clamping NMOS, which is often drawn with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. A modified power-rail ESD clamp circuit is proposed to solve this problem. The proposed power-rail ESD clamp circuit can provide high enough chip-level ESD robustness, and without suffering the latchup-like failure during the system-level ESD test.

A transient triggered bipolar clamp for electrostatic discharge protection in SiGe BiCMOS technologies

“…. Typically power supply ramp rates of 1-100 Ils are utilized to analyze the clamp mis-triggering behavior [7][8]. Figure 3 …”

Analysis of a Parasitic-Diode-Triggered Electrostatic Discharge Protection Circuit for 12 V Applications

“…These advances have hitherto resulted in further miniaturization and performance improvement, but malfunctions and breakdowns owing to electrostatic discharges under normal operating conditions have become critical issues [1]. Therefore, novel electrostatic discharge protection circuits need to be developed.…”

“…Proposed ESD Protection Circuit 1. Circuit Simulation Figure 1 shows a cross-section of the proposed ESD protection circuit and its equivalent circuit.…”

SCR-based ESD protection device with low trigger and high robustness for I/O clamp

“…Electrostatic Discharge (ESD) is one of the most important reliability issues in CMOS integrated circuit (IC) products [1]. As technology scales down, the ESD phenomenon has become a greater threat for deep-sub-micron ICs, due to their thinner gate oxide and shallow junction depths.…”