Investigation of Polysilicon Thin-Film Transistor Technology for RF Applications

Fast flexible electronics with strained silicon nanomembranes

“…The f max value sets a new speed record for Si-based TFTs fabricated on plastic substrates, even though critical dimensions of the strained channel are larger than the previously reported devices30 and a relatively thick gate dielectric (120 nm) is used. Considering biomedical wireless devices typically operating at 400 MHz32, for which both the strained-channel transistor (this work, on plastic) and poly-Si transistors (on glass) having a f max of 3.5 GHz33 can be used, the strained transistor consumes roughly two orders less power than the poly-Si transistor, as indicated by points A and B in Figure 3f(ii). As a comparison, the unstrained reference TFT with identical dimensions has f T and f max of 3.3 GHz and 10.3 GHz, respectively.…”

The 1‐V 2.4 GHz low‐spur fractional‐N frequency synthesizer chip design with exploiting randomly selected PFD and sub‐sampling charge pump technology

“…Measured results of the prototype illustrate that the proposed PLL is comparable to recently published papers and achieves a wide tuning range from 2.235 to 2.579 GHz corresponding to 14.3%, a power consumption of 9 mW, a reference spur of 270.4 dBc at 25 MHz offset, a phase noise of 2113.17 dBc/Hz at 1 MHz offset from 2.41 GHz and the chip area is only 0.695 mm 2 . Combline and interdigital type bandpass filters (BPFs) have been widely used in various microwave and millimeter wave applications due to their compactness, good stopband and selectivity performance, and relative ease of integration [1,2].Conversely, the substrate integrated waveguide (SIW) technology, formed using two linear arrays of metal vias embedded in a dielectric substrate to connect two metal plates (and hence, forming the electric sidewalls of the waveguide), has been proven to be useful to design compact size, high performance, lowcost integrated waveguide filters [3][4][5][6][7][8][9]. Therefore, realization of SIW-based combline and interdigital BPFs are important and can meet the stringent filtering requirements of recent wireless communication and radar applications [10].…”

“…A CP current mismatch calibration to reduce reference spurs is in [5], however, the chip is complicate and consumes high power of 28.8 mW. From the discussion in [6], we can find that reducing voltage-controlled oscillator (VCO) gain, K VCO and ripple on the controlled voltage, A m , can minimize the spur shown in (1).…”

Improving the Gate-Induced Drain Leakage and On-State Current of Fin-Like Thin Film Transistors with a Wide Drain

“…Polycrystalline silicon (poly-Si) thin film transistors (TFTs) [1][2][3][4] and oxide semiconductor TFTs [5][6][7][8] are suitable for use in system-on-panels (SoP) or system-on-glass (SoG) displays because of their higher electron mobility compared with that of amorphous silicon (a-Si). The attraction of using poly-Si TFTs in displays lies in their ability to integrate peripheral functional components such as a controller, a high-voltage driver, and memory into the display panel.…”