Investigation of the non-linear input capacitance in LDMOS transistors and its contribution to IMD and phase distortion

Bengtsson, Olof; Vestling, Lars; Olsson, Jörgen

doi:10.1016/j.sse.2008.03.001

Cited by 4 publications

(3 citation statements)

References 13 publications

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“…Various power gains as a function of frequency F I G U R E 1 8 Current gain h 21 , voltage gain A v , and Rollett stability factor K as a function of frequency region emerges, as the pinched-off channel potential does not increase. 40 The results, plotted in Figure 12, show that at high V GS , overshoot exceeds the SOA range of the drain bias. However, the parasitic capacitances decouple, when V GS $ V gmpeak , and V DS is high enough to meet the saturation regime.…”

Section: Small-ac and Rf Resultsmentioning

confidence: 97%

Process and performance optimization of Triple‐RESURF LDMOS with Trenched‐Gate

Houadef

Djezzar

2021

Int J RF Microw Comput Aided Eng

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In this article, we investigate by TCAD simulation, the combination triple reduced surface field (triple-RESURF) and trenched-gate to design an n-type laterally diffused metal-oxide-semiconductor (LDMOS) transistor with high performance. While similar structures reported in the literature, on the one hand, use either the triple-RESURF or trenched-gate at once, on the other hand, those features require at least one additional mask each. We have been able to achieve both features in one transistor with only eight masks at the front-end of line (FEOL), and one less annealing. Therefore, our proposition will be cheaper and provide better performance. The structure is obtained by re-organizing the process steps, re-using other existing masks, and exploiting positive and negative photoresist photolithography. The resulting specific on-state resistance (R ON,SP ) is 94 mΩmm 2 , and the breakdown voltage (BV) is 71 V. But, most importantly a high transconductance (g m ) at high gate voltages, with acceptable off-state leakage current (I off ), which translates into better RF performance overall than what is reported in the literature. The maximum oscillation frequency (f MAX ) and cutoff frequency (f T ) could reach up to 76 and 43 GHz, respectively. Our device targets fully integrated IoT ASICs that require power amplifiers.

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Section: Small-ac and Rf Resultsmentioning

confidence: 97%

Process and performance optimization of Triple‐RESURF LDMOS with Trenched‐Gate

Houadef

Djezzar

2021

Int J RF Microw Comput Aided Eng

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“…The research of linearity of RF LDMOS focuses on the linearity of capacitance and transconductance. Paper [2] studied the effects of input capacitance on intermodulation distortion (IMD) and AM-PM distortion under the two-tone signal input of class A power amplifier from the simulation point of view. Paper [3] revealed that the low-frequency IMD related to the nonlinearity of transconductance, while the high-frequency IMD related to the nonlinearity of transconductance and capacitor.…”

Section: Introductionmentioning

confidence: 99%

Improving Linearity and Robustness of RF LDMOS by Mitigating Quasi-Saturation Effect

Song

2019

Active and Passive Electronic Components

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This paper discusses linearity and robustness together for the first time, disclosing a way to improve them. It reveals that the nonlinear transconductance with device working at quasi-saturation region is significant factor of device linearity. The peak electric field is the root cause of electron velocity saturation. The high electric field at the drift region near the drain will cause more electronhole pairs generated to trigger the parasitic NPN transistor turn-on, which may cause failure of device. Devices with different drift region doping are simulated with TCAD and measured. With LDD4 doping, the peak electric field in the drift region is reduced; the linear region of the transconductance is broadened. The adjacent channel power ratio is decreased by 2 dBc; 12% more power can be discharged before the NPN transistor turn-on, indicating a better linearity and robustness.

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“…The effects of the dummy gate on breakdown voltage and hot carrier effect for the RF-LDMOS devices have been under study in the research community for several years [2][3] [4]. On the other hand, special capacitance behaviors of this kind of devices have also been widely discussed in [5][6] [7], but these works are restricted to study on design of non-uniformly doped channel or drift region, without investigating influences of the dummy gate on Cgd. Moreover, the introduction of the dummy gate will unavoidably influence other capacitance components than Cgd, such as input capacitance Cgs and output capacitance Cds.…”

Section: Introductionmentioning

confidence: 99%

Effect of the Dummy Gate on the Capacitance Characteristics of the LDMOSFETs

Zhu¹,

Fu²,

Wang³

et al. 2010

ECS Trans.

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In this article the impact of geometrical parameters of the dummy gate on capacitance characteristics for RF-LDMOS transistors is analyzed and studied by using a 2-D numerical TCAD process and device simulator. Firstly, the device structure and fabrication process are described. Then measured and simulated capacitance characteristics of the fabricated RF-LDMOS transistors are compared, confirming the effectiveness of the TCAD simulations. On the basis of this, further extensive simulations on the device capacitance characteristics for varying thickness of the oxide layer under and beside the dummy gate (tfox) and length of the dummy gate over n-drift region (Lf) are carried out. Based on these simulation results, the effects of the dummy gate on various capacitance components are analyzed and discussed, indicating that feedback capacitances can be effectively reduced by the introduction of the dummy gate to the device, nevertheless, at the expense of increased output and input capacitances. For this reason, the key geometry parameters of the dummy gate have to be traded off in order to optimize device design.

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Investigation of the non-linear input capacitance in LDMOS transistors and its contribution to IMD and phase distortion

Cited by 4 publications

References 13 publications

Process and performance optimization of Triple‐RESURF LDMOS with Trenched‐Gate

Process and performance optimization of Triple‐RESURF LDMOS with Trenched‐Gate

Improving Linearity and Robustness of RF LDMOS by Mitigating Quasi-Saturation Effect

Effect of the Dummy Gate on the Capacitance Characteristics of the LDMOSFETs

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