(Invited) Cutting-Edge Epitaxial Processes for Sub 3 Nm Technology Nodes: Application to Nanosheet Stacks and Epitaxial Wrap-Around Contacts

Abstract

This work reports on low temperature epitaxial growth solutions for the processing of advanced CMOS devices beyond the 3 nm technological node. The complex stacking of highly compositionally contrasted strained group IV materials is first demonstrated at 500C. It enables the formation of active nanosheet channels with bottom isolation, necessary for ultimate transistor scaling. Using high order Si and Ge precursors also offers great opportunities for the epitaxy of advanced source/drain materials. It allows achieving hole active concentrations as high as 1.3x10 21 cm -3 in in-situ B-doped Si0.5Ge0.5, providing Ti / SiGe:B contacts with low specific resistivity. Grown at temperatures as low as 400C, the epilayers deposit in a conformal manner, thereby wrapping high aspect ratio 3-dimensional structures and maximizing the contact areas, being an additional option to further decrease device access resistances. As an alternative to B-doping only, we also demonstrate uniformly Ga-doped materials with concentrations ~ 1x10 20 cm -3 . B and Ga are finally combined to co-dope SiGe and further reduce the Ti / p-SiGe contact resistivity.

Microsecond non-melt UV laser annealing for future 3D-stacked CMOS

“…The maximum Rsq degradation ratio was ~5 % in the studied DA timescale, encouraging UV-LA integration into different stages of a 3D-stacked transistor fabrication flow to boost chip performance further. Although the level of active carrier concentration achieved in this work meets the current requirement of the state-of-the-art CMOS technologies, [45][46] the formation of donor-V complexes (e.g., AsnV) might restrict its additional enhancement. Then, the use of alternative doping elements, especially the chalcogens such as selenium 47 and tellurium, 48 may provide a solution.…”

(Digital Presentation) Selective SiGe Vapor Etching Using Br2 in View of Nanosheet Device Isolation

“…Epitaxial growth of Si/Si0.5Ge0.5/multi-[Si1-xGex/Si] layers Our fabrication scheme for the fabrication of bottom isolation starts with the epitaxial growth of epitaxial Si/Si0.5Ge0.5/multi-[Si1-xGex/Si] stacks where the bottom Si0.5Ge0.5 layer is later replaced by a SiN/SiCO isolation (4). In case of GAA devices without bottom isolation, the Si/Si1-xGex multi-stack can be grown using conventional process gases (4,8,9). With bottom isolation, the epi-stack starts with a Ge-rich Si1-yGey layer.…”

“…Bottom dielectric isolation has been proposed to circumvent the junction isolation trade-off between punch-through suppression on the one hand and junction leakage and capacitance on the other hand (3). A typical fabrication scheme includes the epitaxial growth of Si/Si1-yGey/multi-[Si1-xGex/Si] epi stacks (y > x) where the bottom Si1-yGey layer is later replaced by a SiN/SiCO isolation (4). A similar approach is followed for complementary FET (CFET) devices where pFET and nFET are stacked on top of each other with a dielectric isolation in between.…”

“…The selective removal of Si1-yGey requires a great precision in its adjustment, with the risk of experiencing process variabilities and yield issues. Selective SiGe etching is typically done in advanced wet or dry chemistries and is sensitive to both strain in and oxidation of individual layers (4)(5)(6). Also, HCl-based vapor etching has been reported for Corresponding author: roger.loo@imec.be SiGe removal, with high selectivity towards Si (7).…”

Low Temperature Epitaxy of In Situ GaDoped Si1-XGex: Dopant Incorporation, Structural and Electrical Properties

“…The growth has been performed either at 400°C or at 350°C and a pressure of 20 Torr. Non-conventional higher order Si and Ge precursors have been used to maintain an acceptable growth rate at low temperatures (12). Tri-tert-butyl gallium (TTBGa) has been flown in the CVD reactor in order to obtain the in-situ Ga doping.…”