(Invited) Downscaling Issues in Polycrystalline Silicon TFTs

Abstract

Future system-on-panel applications require further performance improvement of circuits based on polycrystalline silicon thin film transistors (TFTs). The biggest leverage in circuit performance can be obtained by reducing channel length from the typical current values of 3-6Pm to 1Pm, or less. Therefore, short channel effects in scaled down polysilicon TFTs will have to be controlled in order to allow proper operation of the circuits. In this work we review a number of specific aspects of the electrical characteristics of short channel devices (channel lengths down to 0.4 Pm) combining electrical characteristics measurements and two-dimensional numerical simulations.

(Invited) Short Channel Effects and Drain Field Relief Architectures in Polysilicon TFTs

“…In order to improve circuit performance, needed for both compensating pixel circuits as well as for integrated drivers, reduction of channel length, from the typical current values of 3 μm to 1 μm or less, is being pursued. As a result, short channel effects [6] and hot carrier induced instability [7] in scaled down self-aligned (SA) polysilicon TFTs become a serious issue, and drain field engineering is mandatory. In this work we review the effects of downscaling the device geometry and, in particular, the kink effect, threshold voltage variations and hot-carrier induced instability are examined in some detail by combining experimental measurements and two-dimensional numerical simulations.…”